23.10.6 TxRST

Name:	TxRST
Offset:	0x0391

Timer External Reset Signal Selection Register


Bit	7	6	5	4	3	2	1	0
				RSEL[4:0]
Access				R/W	R/W	R/W	R/W	R/W
Reset				0	0	0	0	0

Bits 4:0 – RSEL[4:0] External Reset Source Selection

Table 23-4. External Reset Sources
RSEL	Reset Source
`11111`	Reserved
`11110`	PWM2_OUT
`11101`	PWM1_OUT
`11100`	CLB_BLE[14]
`11011`	CLB_BLE[13]
`11010`	CLB_BLE[12]
`11001`	CLB_BLE[11]
`11000`	CLB_BLE[10]
`10111`	CLB_BLE[9]
`10110`	CLB_BLE[8]
`10101`	CLB_BLE[7]
`10100`	CLC4_OUT
`10011`	CLC3_OUT
`10010`	CLC2_OUT
`10001`	CLC1_OUT
`10000`	Reserved
`01111`	C2_OUT
`01110`	C1_OUT
`01101-00110`	Reserved
`00101`	CCP2_OUT
`00100`	CCP1_OUT
`00011-00001`	Reserved
`00000`	Pin selected by T2INPPS

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