25.7.4 Interrupt Enable Set

This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Table 25-5. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
R Readable bit HC Cleared by Hardware(Grey cell)Unimplemented
W Writable bit HS Set by Hardware X Bit is unknown at Reset
K Write to clear S Software settable bit——
Name: INTENSET
Offset: 0x0D
Reset: 0x00
Property: PAC Write-Protection

Bit 76543210 
      DRDYAMATCHPREC 
Access R/WR/WR/W 
Reset 000 

Bit 2 – DRDY Data Ready Interrupt Enable

Writing '0' to this bit has no effect.

Writing '1' to this bit will set the Data Ready bit, which enables the Data Ready interrupt.

ValueDescription
0The Data Ready interrupt is disabled.
1The Data Ready interrupt is enabled.

Bit 1 – AMATCH Address Match Interrupt Enable

Writing '0' to this bit has no effect.

Writing '1' to this bit will set the Address Match Interrupt Enable bit, which enables the Address Match interrupt.

ValueDescription
0The Address Match interrupt is disabled.
1The Address Match interrupt is enabled.

Bit 0 – PREC Stop Received Interrupt Enable

Writing '0' to this bit has no effect.

Writing '1' to this bit will set the Stop Received Interrupt Enable bit, which enables the Stop Received interrupt.

ValueDescription
0The Stop Received interrupt is disabled.
1The Stop Received interrupt is enabled.