13.4.3 Clocks

The PM bus clock (CLK_PM_APB) can be enabled and disabled in the Power Manager, and the default state of CLK_PM_APB can be found in the Peripheral Clock Default State table in the Peripheral Clock Masking section. If this clock is disabled in the Power Manager, it can only be re-enabled by a Reset.

A generic clock (GCLK_MAIN) is required to generate the main clock. The clock source for GCLK_MAIN is configured by default in the generic clock controller, and can be reconfigured by the user if needed. Refer to GCLK – Generic Clock Controller for details.