1 Silicon Issue Summary Legend - Erratum is not applicable. X Erratum is applicable. Peripheral Short Description Valid for Silicon Revision Rev. A Device 2.2.1 IDD Power-Down Current Consumption X 2.2.2 Writing the OSCLOCK Fuse in FUSE.OSCCFG to ‘1’ Prevents Automatic Loading of Calibration Values X 2.2.3 Write Operation Lost if Consecutive Writes to Specific Address Spaces X ADC 2.3.1 Low Latency Mode Must Be Set Before Changing ADC Configuration X 2.3.2 The PGA Initialization Delay Does Not Work Outside Low Latency Mode X 2.3.3 ADC Stays Active in Sleep Modes for Low Latency Mode and Free Running Mode X CCL 2.4.1 The CCL Must be Disabled to Change the Configuration of a Single LUT X CRCSCAN 2.5.1 Running CRC Scan on Part of The Flash is Non-Functional X NVMCTRL 2.6.1 Wrong Reset Value of NVMCTRL.CTRLA Register X TCA 2.7.1 Restart Will Reset Counter Direction in NORMAL and FRQ Mode X TCB 2.8.1 CCMP and CNT Registers Act as 16-Bit Registers in 8-Bit PWM Mode X USART 2.9.1 Start-of-Frame Detection Can Unintentionally Be Triggered in Active Mode X 2.9.2 Receiver Non-Functional after Detection of Inconsistent Synchronization Field X
