11.4.2 Natural Order (Hardware) Priority

When vectored interrupts are enabled and more than one interrupt with the same user specified priority level is requested, the priority conflict is resolved by using a method called “Natural Order Priority”. Natural order priority is a fixed priority scheme that is based on the IVT.

Table 11-2. Interrupt Vector Priority Table
Vector

Number

Interrupt

source

Vector

Number

(cont.)

Interrupt

source

(cont.)

0x0 Software Interrupt 0x2D CLC2
0x1 HLVD (High/Low-Voltage Detect) 0x2E PWM2PR
0x2 OSF (Oscillator Fail) 0x2F PWM2
0x3 CSW (Clock Switching) 0x30 INT1
0x4 NVM 0x31 CWG1 (Complementary Waveform Generator)
0x5 CLC1 (Configurable Logic Cell) 0x32 NCO1 (Numerically Controlled Oscillator)
0x6 CRC (Cyclic Redundancy Check) 0x33 DMA2SCNT
0x7 IOC (Interrupt-On-Change) 0x34 DMA2DCNT
0x8 INT0 0x35 DMA2OR
0x9 ZCD (Zero-Cross Detection) 0x36 DMA2A
0xA AD (ADC Conversion Complete) 0x37 -
0xB ACT (Active Clock Tuning) 0x38 I2C1RX
0xC CM1 (Comparator) 0x39 I2C1TX
0xD SMT1 (Signal Measurement Timer) 0x3A I2C1
0xE - 0x3B I2C1E
0xF SMT1PWA 0x3C -
0x10 ADT 0x3D CLC3
0x11 - 0x13 - 0x3E PWM3PR
0x14 DMA1SCNT (Direct Memory Access) 0x3F PWM3
0x15 DMA1DCNT 0x40 U2RX
0x16 DMA1OR 0x41 U2TX
0x17 DMA1A 0x42 U2E
0x18 SPI1RX (Serial Peripheral Interface) 0x43 U2
0x19 SPI1TX 0x44 -
0x1A SPI1 0x45 CLC4
0x1B TMR2 0x46 -
0x1C TMR1 0x47 SCAN
0x1D TMR1G 0x48 U3RX
0x1E CCP1 (Capture/Compare/PWM) 0x49 U3TX
0x1F TMR0 0x4A U3E
0x20 U1RX 0x4B U3
0x21 U1TX 0x4C DMA3SCNT
0x22 U1E 0x4D DMA3DCNT
0x23 U1 0x4E DMA3OR
0x24 TMR3 0x4F DMA3A
0x25 TMR3G 0x50 INT2
0x26 PWM1PR 0x51 -
0x27 PWM1 0x52 -
0x28 SPI2RX 0x53 TMR4
0x29 SPI2TX 0x54 DMA4SCNT
0x2A SPI2 0x55 DMA4DCNT
0x2B - 0x56 DMA4OR
0x2C CM2 (Comparator) 0x57 DMA4A

The natural order priority scheme goes from high-to-low with increasing vector numbers, with 0 being the highest priority and decreasing from there.

For example, when two concurrently occurring interrupt sources that are both designated high priority, using the IPRx register will be resolved using the natural order priority (i.e., the interrupt with a lower corresponding vector number will preempt the interrupt with the higher vector number).

The ability for the user to assign every interrupt source to high- or low-priority levels means that the user program can give an interrupt with a low natural priority, a higher overall priority level.