11.13.27 PIR9

Peripheral Interrupt Request Register 9

Note:

Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit, or the global enable bit. User software must ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
U3IF is a read-only bit. To clear the interrupt condition, all bits in the U3UIR register must be cleared.
U3EIF is a read-only bit. To clear the interrupt condition, all bits in the U3ERR register must be cleared.
U3TXIF and U3RXIF are read-only bits and cannot be set/cleared by software.

Name:	PIR9
Address:	0x4BC


Bit	7	6	5	4	3	2	1	0
	DMA3AIF	DMA3ORIF	DMA3DCNTIF	DMA3SCNTIF	U3IF	U3EIF	U3TXIF	U3RXIF
Access	R/W/HS	R/W/HS	R/W/HS	R/W/HS	R	R	R	R
Reset	0	0	0	0	0	0	0	0

Bit 7 – DMA3AIF DMA3 Abort Interrupt Flag

Value	Description
1	Interrupt has occurred (must be cleared by software)
0	Interrupt event has not occurred

Bit 6 – DMA3ORIF DMA3 Overrun Interrupt Flag

Value	Description
1	Interrupt has occurred (must be cleared by software)
0	Interrupt event has not occurred

Bit 5 – DMA3DCNTIF DMA3 Destination Count Interrupt Flag

Value	Description
1	Interrupt has occurred (must be cleared by software)
0	Interrupt event has not occurred

Bit 4 – DMA3SCNTIF DMA3 Source Count Interrupt Flag

Value	Description
1	Interrupt has occurred (must be cleared by software)
0	Interrupt event has not occurred

Bit 3 – U3IF UART3 Interrupt Flag⁽²⁾

Value	Description
1	Interrupt has occurred
0	Interrupt event has not occurred

Bit 2 – U3EIF UART3 Framing Error Interrupt Flag⁽³⁾

Value	Description
1	Interrupt has occurred
0	Interrupt event has not occurred

Bit 1 – U3TXIF UART3 Transmit Interrupt Flag⁽⁴⁾

Value	Description
1	Interrupt has occurred
0	Interrupt event has not occurred

Bit 0 – U3RXIF UART3 Receive Interrupt Flag⁽⁴⁾

Value	Description
1	Interrupt has occurred
0	Interrupt event has not occurred

Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit, or the global enable bit. User software must ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. U3IF is a read-only bit. To clear the interrupt condition, all bits in the U3UIR register must be cleared. U3EIF is a read-only bit. To clear the interrupt condition, all bits in the U3ERR register must be cleared. U3TXIF and U3RXIF are read-only bits and cannot be set/cleared by software.