15.5.2 Channel n Generator Selection

Each channel can be connected to one event generator. Not all generators can be connected to all channels. Refer to the table below to see which generator sources can be routed onto each channel and the generator value to be written to EVSYS.CHANNELn to achieve this routing. Writing the value 0x00 to EVSYS.CHANNELn turns the channel off.

Refer to the Peripheral Overview section for the available number of Event System channels.

Name:	CHANNELn
Offset:	0x10 + n*0x01 [n=0..5]
Reset:	0x00
Property:	-


Bit	7	6	5	4	3	2	1	0
	CHANNELn[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 7:0 – CHANNELn[7:0] Channel Generator Selection

The specific generator name corresponding to each bit group configuration is given by combining Peripheral and Output from the table below in the following way: PERIPHERAL_OUTPUT.


GENERATOR			Async/Sync	Description	Channel Availability
Value	Name
Value	Peripheral	Output
`0x01`	UPDI	SYNCH	Sync	Rising edge of SYNCH character detection	All channels
`0x06`	RTC	OVF	Async	Counter overflow	All channels
`0x07`		CMP		Compare match	All channels
`0x08`		PIT_DIV8192		Prescaled RTC clock divided by 8192	Even numbered channels only
`0x09`		PIT_DIV4096		Prescaled RTC clock divided by 4096
`0x0A`		PIT_DIV2048		Prescaled RTC clock divided by 2048
`0x0B`		PIT_DIV1024		Prescaled RTC clock divided by 1024
`0x08`		PIT_DIV512		Prescaled RTC clock divided by 512	Odd numbered channels only
`0x09`		PIT_DIV256		Prescaled RTC clock divided by 256
`0x0A`		PIT_DIV128		Prescaled RTC clock divided by 128
`0x0B`		PIT_DIV64		Prescaled RTC clock divided by 64
`0x10`	CCL	LUT0	Async	LUT output level	All channels
`0x11`		LUT1
`0x12`		LUT2
`0x13`		LUT3
`0x20`	AC0	OUT	Async	Comparator output level	All channels
`0x24`	ADC0	RES	Sync	Result ready	All channels
`0x25`		SAMP		Sample ready
`0x26`		WCMP		Window compare match
`0x40-0x47`	PORTA	PIN0-PIN7	Async	PORTA PIN0-PIN7 level⁽²⁾	CHANNEL0 and CHANNEL1 only
`0x48-0x4F`	PORTA	PIN0-PIN7	Async	PORTA PIN0-PIN7 level⁽²⁾	CHANNEL2 and CHANNEL3 only
`0x40-0x47`	PORTB	PIN0-PIN7	Async	PORTB PIN0-PIN7 level⁽²⁾	CHANNEL4 and CHANNEL5 only
`0x48-0x4F`	PORTB	PIN0-PIN7	Async	PORTB PIN0-PIN7 level⁽²⁾	CHANNEL0 and CHANNEL1 only
`0x40-0x47`	PORTC ⁽¹⁾	PIN0-PIN7	Async	PORTC PIN0-PIN7 level ⁽²⁾	CHANNEL2 and CHANNEL 3 only
`0x48-0x4F`	PORTC ⁽¹⁾	PIN0-PIN7	Async	PORTC PIN0-PIN7 level ⁽²⁾	CHANNEL4 and CHANNEL5 only
`0x60`	USART0	XCK	Sync	Clock signal in SPI Host mode and synchronous USART Host mode	All channels
`0x61`	USART1	XCK	Sync		All channels
`0x68`	SPI0	SCK	Sync	SPI host clock signal	All channels
`0x80`	TCA0	OVF_LUNF	Sync	Normal mode: Overflow Split mode: Low byte timer underflow	All channels
`0x81`		HUNF	Sync	Normal mode: Not available Split mode: High byte timer underflow
`0x84`		CMP0_LCMP0	Sync	Normal mode: Compare Channel 0 match Split mode: Low byte timer Compare Channel 0 match
`0x85`		CMP1_LCMP1	Sync	Normal mode: Compare Channel 1 match Split mode: Low byte timer Compare Channel 1 match
`0x86`		CMP2_LCMP2	Sync	Normal mode: Compare Channel 2 match Split mode: Low byte timer Compare Channel 2 match
`0xA0`	TCB0	CAPT	Sync	CAPT flag set⁽³⁾	All channels
`0xA1`	TCB0	OVF	Sync	OVF flag set	All channels
`0xA2`	TCB1	CAPT	Sync	CAPT flag set⁽³⁾	All channels
`0xA3`	TCB1	OVF	Sync	OVF flag set	All channels

Note:

Not all peripheral instances are available for all pin counts. Refer to the Peripherals and Architecture section for details.
An event from the PORT pin will be zero if the input driver is disabled.
The operational mode of the timer decides when raising the CAPT flag. Refer to the TCB section for details.

ATtiny3224/3226/3227

15.5.2 Channel n Generator Selection

Bits 7:0 – CHANNELn[7:0] Channel Generator Selection