16.14.3 TRISx

Tri-State Control Register
Important:
  • The TRIS bit associated with the MCLR pin is read-only and the value is ‘1
  • Refer to the “Pin Allocation Table” for details about MCLR pin and pin availability per port
  • Unimplemented bits will read back as ‘0
Name: TRISx

Bit 76543210 
 TRISx7TRISx6TRISx5TRISx4TRISx3TRISx2TRISx1TRISx0 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 11111111 

Bits 0, 1, 2, 3, 4, 5, 6, 7 – TRISxn Port I/O Tri-state Control

ValueDescription
1 PORTx output driver is disabled. PORTx pin configured as an input (tri-stated).
0 PORTx output driver is enabled. PORTx pin configured as an output.
The TRIS bit associated with the MCLR pin is read-only and the value is ‘1’ Refer to the “Pin Allocation Table” for details about MCLR pin and pin availability per port Unimplemented bits will read back as ‘0’