8.6.4 CONFIG4

Configuration Word 4

Note:

The LVP bit cannot be written (to zero) while operating from the LVP programming interface. The purpose of this rule is to prevent the user from dropping out of LVP mode while programming from LVP mode or accidentally eliminating LVP mode from the Configuration state.
Once protection is enabled through ICSP or a self-write, it can only be reset through a Bulk Erase.
Applicable only if SAFEN = 0.
Applicable only if BBEN = 0.
BBSIZE[2:0] bits can only be changed when BBEN = 1. Once BBEN = 0, BBSIZE[2:0] can only be changed through a Bulk Erase.
The maximum Boot Block size is half of the user program memory size. Any selection that will exceed the half of a device’s program memory will default to a maximum Boot Block size of half PFM.

Name:	CONFIG4
Offset:	0x800A


Bit	15	14	13	12	11	10	9	8
			LVP		WRTSAF	WRTD	WRTC	WRTB
Access			R/W		R/W	R/W	R/W	R/W
Reset			1		1	1	1	1


Bit	7	6	5	4	3	2	1	0
	WRTAPP			SAFEN	BBEN	BBSIZE[2:0]
Access	R/W			R/W	R/W	R/W	R/W	R/W
Reset	1			1	1	1	1	1

Bit 13 – LVP Low-Voltage Programming Enable⁽¹⁾

Value	Description
1	Low-Voltage Programming is enabled. MCLR/V_PP pin function is MCLR. The MCLRE bit is ignored.
0	High voltage (HV) on MCLR/V_PP must be used for programming

Bit 11 – WRTSAF Storage Area Flash (SAF) Write Protection^(2,3)

Value	Description
1	SAF is not write-protected
0	SAF is write-protected

Bit 10 – WRTD Data EEPROM Write Protection

Value	Description
1	Data EEPROM is not write-protected
0	Data EEPROM is write-protected

Bit 9 – WRTC Configuration Registers Write Protection⁽²⁾

Value	Description
1	Configuration registers are not write-protected
0	Configuration registers are write-protected

Bit 8 – WRTB Boot Block Write Protection^(2,4)

Value	Description
1	Boot Block is not write-protected
0	Boot Block is write-protected

Bit 7 – WRTAPP Application Block Write Protection⁽²⁾

Value	Description
1	Application Block is not write-protected
0	Application Block is write-protected

Bit 4 – SAFEN Storage Area Flash (SAF) Enable⁽²⁾

Value	Description
1	SAF is disabled
0	SAF is enabled

Bit 3 – BBEN Boot Block Enable⁽²⁾

Value	Description
1	Boot Block is disabled
0	Boot Block is enabled

Bits 2:0 – BBSIZE[2:0] Boot Block Size Selection^(5,6)

Table 8-1. Boot Block Size
BBEN	BBSIZE	End Address of Boot Block	Boot Block Size (words)
BBEN	BBSIZE	End Address of Boot Block	PIC16F181x4	PIC16F181x5
`1`	`xxx`	–	–
`0`	`111`	01FFh	512
`0`	`110`	03FFh	1024
`0`	`101`	07FFh	2048
`0`	`100`	0FFFh	–⁽⁶⁾	4096
`0`	`011`	1FFFh	–⁽⁶⁾
`0`	`010`	3FFFh	–⁽⁶⁾
`0`	`001`	3FFFh	–⁽⁶⁾
`0`	`000`	3FFFh	–⁽⁶⁾

The LVP bit cannot be written (to zero) while operating from the LVP programming interface. The purpose of this rule is to prevent the user from dropping out of LVP mode while programming from LVP mode or accidentally eliminating LVP mode from the Configuration state. Once protection is enabled through ICSP or a self-write, it can only be reset through a Bulk Erase. Applicable only if SAFEN = 0. Applicable only if BBEN = 0. BBSIZE[2:0] bits can only be changed when BBEN = 1. Once BBEN = 0, BBSIZE[2:0] can only be changed through a Bulk Erase. The maximum Boot Block size is half of the user program memory size. Any selection that will exceed the half of a device’s program memory will default to a maximum Boot Block size of half PFM.