20.4.3 PMD2

PMD Control Register 2
Name: PMD2
Offset: 0x010E

Bit 76543210 
 CLC3MDCLC2MDCLC1MDCWG1MDNCO1MDPWM4MDPWM3MDPWM2MD 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bit 7 – CLC3MD Disable CLC3

ValueDescription
1 CLC3 disabled
0 CLC3 enabled

Bit 6 – CLC2MD Disable CLC2

ValueDescription
1 CLC2 disabled
0 CLC2 enabled

Bit 5 – CLC1MD Disable CLC1

ValueDescription
1 CLC1 disabled
0 CLC1 enabled

Bit 4 – CWG1MD Disable CWG1

ValueDescription
1 CWG1 disabled
0 CWG1 enabled

Bit 3 – NCO1MD Disable NCO1

ValueDescription
1 NCO1 disabled
0 NCO1 enabled

Bit 2 – PWM4MD Disable PWM4

ValueDescription
1 PWM4 disabled
0 PWM4 enabled

Bit 1 – PWM3MD Disable PWM3

ValueDescription
1 PWM3 disabled
0 PWM3 enabled

Bit 0 – PWM2MD Disable PWM2

ValueDescription
1 PWM2 disabled
0 PWM2 enabled