20.1.2.5.1 QoS AXI Initiator

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The QoS feature allows bandwidth to be shared among the fabric initiators while accessing DDR. To share bandwidth, an AXI initiator (referred as the QoS initiator) is connected internally at the AXI switch that performs the DDR access. This AXI initiator, which is hidden from the user, performs DDR access controlled through QoS AXI Initiator parameters. The QoS is enabled only when DDR is enabled.

You can change the QoS parameter values using vsim commands while launching the simulation. To do so, see the following table.

Table 20-14. MSS QoS AXI Initiator Parameters
Parameter	Description	Default Value
QOS_AXI_CLKS	Number of AXI clocks at which QoS initiator performs read/write AXI transactions with DDR. To change the value of this parameter, use the following `vsim` command: `vsim -L polarfire -L presynth -t 1ps –g` `QOS_AXI_CLKS = 10000 presynth.tb`	5000
QOS_START_ADDRESS	Base address for QoS operation. Change this address if the same address region is being used by another application through FIC. To avoid contention between QoS and FIC accessing the same DDR region, shift the QoS access region to an unused address region. To change the value of this parameter, use the following `vsim` command: For 38-bit: `vsim -L polarfire -L presynth -t 1ps -gQOS_START_ADDRESS=38'h1600000000 presynth.tb` For 32-bit: (also need to change DDR_ADDRESS_REGION for 32-bit) `vsim -L polarfire -L presynth -t 1ps -gQOS_START_ADDRESS=32'hcd000000 -gDDR_ADDRESS_REGION=0 presynth.tb`	38'h00_C000_0000
NO_OF_QOS_TRANSACTIONS	Number of burst read/write transactions performed by QoS at regular or cyclic intervals of QOS_AXI_CLKS. If set to zero, QoS does not perform any AXI transactions to DDR and the entire bandwidth is allocated to FICs. Note: Make sure the QOS_AXI_CLKS value is much greater than the finish time of all QoS AXI transactions. The smallest burst size typically uses: 10 AXI clocks for read or write burst transaction with DQ = 16. 20 AXI clocks for read or write burst transaction with DQ = 16. To change the value of this parameter, use the following `vsim` command: `vsim -L polarfire -L presynth -t 1ps -gNO_OF_QOS_TRANSACTIONS=512 presynth.tb`	128 when DDR is used.

The following shows an example of a simulation log where a fabric QoS initiator accesses DDR with number of QoS transactions set to ONE.

#  
# QoS Write Transactions          1 Completed
# QoS Read Transactions          1 Completed
# Writing to DDR3 Memory @ rank = 0, bank = 00, row = 00000, col = 00000000, data = 12345678
# Writing to DDR3 Memory @ rank = 0, bank = 00, row = 00000, col = 00000001, data = aabbccdd
# Writing to DDR3 Memory @ rank = 0, bank = 00, row = 00000, col = 00000002, data = 12355577
# Writing to DDR3 Memory @ rank = 0, bank = 00, row = 00000, col = 00000003, data = aabbccdd
# Writing to DDR3 Memory @ rank = 0, bank = 00, row = 00000, col = 00000004, data = 12365476
# Writing to DDR3 Memory @ rank = 0, bank = 00, row = 00000, col = 00000005, data = aabbccdd
# Writing to DDR3 Memory @ rank = 0, bank = 00, row = 00000, col = 00000006, data = 12375375
# Writing to DDR3 Memory @ rank = 0, bank = 00, row = 00000, col = 00000007, data = aabbccdd
# Reading from DDR3 Memory @ rank = 0, bank = 00, row = 00000, col = 00000000, data = 12345678
# Reading from DDR3 Memory @ rank = 0, bank = 00, row = 00000, col = 00000001, data = aabbccdd
# Reading from DDR3 Memory @ rank = 0, bank = 00, row = 00000, col = 00000002, data = 12355577
# Reading from DDR3 Memory @ rank = 0, bank = 00, row = 00000, col = 00000003, data = aabbccdd
# Reading from DDR3 Memory @ rank = 0, bank = 00, row = 00000, col = 00000004, data = 12365476
# Reading from DDR3 Memory @ rank = 0, bank = 00, row = 00000, col = 00000005, data = aabbccdd
# Reading from DDR3 Memory @ rank = 0, bank = 00, row = 00000, col = 00000006, data = 12375375
# Reading from DDR3 Memory @ rank = 0, bank = 00, row = 00000, col = 00000007, data = aabbccdd