Clock and Strobe Relationships

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This section describes the relationship between the clock and strobe signals used in the MSS DDR interface. Each signal plays a specific role in timing, synchronization, and data integrity. The following figure shows the clock and strobe relationship.

Figure 20-40. Clock and Strobe Relationships

The following clocks and strobe signals are used in the MSS DDR interface:

REF CLK (Reference Clock): REF CLK provides reference frequency for PLLs (Phase-Locked Loops) and clock generation circuits within the MSS. Its is used as the input to generate other system clocks (SYS_CLK and HS-IO_CLK) through PLLs.
HS-IO_CLK (High-Speed IO Clock): HS-IO_CLK drives the high-speed IO logic, including the DDR controller and PHY. Derived from REF CLK through PLLs. It is used to synchronize the DDR interface logic and may serve as the source for BCLK and other DDR-related clocks.
BCLK 90 and BCLK 270 (Byte Clock at 90° and 270° Phase): These are phase-shifted versions of the byte clock (BCLK), used for precise timing alignment in DDR operations. BCLK 90 is BCLK shifted by 90 degrees, often used for sampling or aligning data transitions. BCLK 270 is BCLK shifted by 270 degrees, providing another timing reference for data capture or strobe alignment. Both are derived from HS-IO_CLK or SYS_CLK through PLLs or delay lines and are essential for DDR training (for example, centering the data eye).
SYS_CLK (System Clock): SYS_CLK is the main clock for the MSS and system logic. Derived from REF CLK, it may be asynchronous to DDR clocks but is used for overall system timing and may interact with the DDR controller for configuration and status monitoring.
DQS (Data Strobe): DDR memory uses DQS as a strobe signal to indicate when data (DQ) is valid during read and write operations. DQS is edge-aligned or center-aligned with DQ, depending on the DDR mode. The timing of DQS is calibrated during DDR training using BCLK 90/270 and HS-IO_CLK to ensure reliable data capture.
DQS_W (Write Data Strobe): Specific to write operations, DQS_W is the strobe signal sent from the controller to the DDR memory to indicate valid write data. Synchronized with the write data (DQ) and aligned using the same clocking infrastructure (HS-IO_CLK, BCLK 90/270). Its timing is critical for successful write leveling and training.

The following table lists the overall correlation and timing Architecture.

Table 20-22. Overall Correlation of Clocks and Strobes
Signal	Source/Derived From	Role in DDR Interface	Correlation/Interaction
REF CLK	External oscillator	PLL reference, clock source	Feeds PLLs for SYS_CLK, HS-IO_CLK
HS-IO_CLK	PLL (from REF CLK)	DDR controller/PHY timing	Source for BCLK, DQS, DQS_W
BCLK 90/270	HS-IO_CLK	Phase-shifted DDR timing	Used for data/strobe alignment
SYS_CLK	PLL (from REF CLK)	System logic timing	May be asynchronous to DDR clocks
DQS	DDR controller/PHY	Data strobe for reads/writes	Aligned using BCLK 90/270, HS-IO_CLK
DQS_W	DDR controller/PHY	Write data strobe	Aligned using BCLK 90/270, HS-IO_CLK

REF CLK is the master reference for all clocks. PLLs generate HS-IO_CLK and SYS_CLK, which are then used to derive phase-shifted clocks (BCLK 90/270) for precise DDR timing. During DDR training, the controller uses BCLK 90/270 to adjust the timing of DQS and DQS_W, ensuring that data is sampled at the optimal point (center of the data eye). SYS_CLK runs the MSS and interacts with the DDR controller for configuration, but actual DDR data transfers are synchronized to HS-IO_CLK and its derivatives.