20.2.2.3.5.2 DDR Controller Options Impacting Training

DQDQS start training window offset

This option determines the initial phase offset between the Data (DQ) and Data Strobe (DQS) signals during the DDR training process. This offset is crucial for aligning the DQ and DQS signals so that data can be reliably captured during read and write operations.

During DDR initialization, the controller performs a series of training steps, including read leveling and gate training. The DQDQS offset sets the starting point for the controller to search for the optimal sampling window where DQ and DQS are properly aligned. If the offset is not set correctly, the training algorithm may start outside the valid data window, causing the controller to miss the optimal alignment. This can result in training failures or marginal operation.

The optimal value for the DQDQS offset is also dependent on the board layout, specifically the trace lengths and skew between DQ and DQS signals. Mismatched trace lengths can reduce the valid window for DQ/DQS alignment. recommend adjusting the DQDQS Start Training Window Offset in small increments (for example, values from 1 to 8) and observing the training results. The goal is to find a value where training consistently passes across all lanes and power cycles. Follow these guidelines:

Begin with the default value provided by the MSS Configurator or reference design. If training fails, incrementally adjust the offset and retest.
Use the mpfs-hal-ddr-demo to test DDR training and capture logs for analysis.
Use the Memory Log Analyzer tool to interpret training logs and identify if the DQDQS window is too small or misaligned.
For each offset value tested, record whether training passes and note any marginal or failing lanes. Select the value that provides the most robust and consistent results.

Vref CA (as % of vddi)

Reference Voltage for Command/Address signals (Vref CA), is expressed as a percentage of the DDR I/O supply voltage (VDDI). Vref CA is used by the DDR memory and controller to interpret logic levels on the command and address lines. If Vref CA is set too high or too low relative to Vddi, the DDR controller and memory device may misinterpret signals, leading to command or address errors.

During DDR training, the controller sends initialization commands and address sequences to the memory device. Accurate interpretation of these signals is essential for successful training steps such as mode register set (MRS), ZQ calibration, and other initialization routines. An incorrect Vref CA setting can cause training failures, as the memory may not recognize commands or addresses correctly.

Typically, set Vref CA (as % of vddi) to 50% of Vddi, which is the JEDEC standard for most DDR devices. Adjust the Vref CA value if you have signal integrity analysis or manufacturer guidance.

Vref data (as % of vddi)

Vref data is the reference voltage used by the DDR memory and controller to interpret the logic levels on the data (DQ) lines. It is set as a percentage of the DDR I/O supply voltage (VDDI).

During read/write leveling and data eye training, the controller adjusts timing and voltage thresholds to maximize the data eye. If Vref data is set too high or too low, the data eye shrinks or shifts, increasing the possibility of bit errors and training failures.

During training, the DDR controller uses Vref data to calibrate the optimal sampling point for data. An improper Vref data setting can cause the controller to misinterpret data, leading to training failure.

Advanced CA training

This option enables enhanced algorithms for Command/Address (CA) training, going beyond the basic CA training sequence. It improves the alignment and timing margins of the CA signals relative to the DDR clock, especially in challenging board layouts or at higher memory speeds.

When enabled, the controller uses advanced routines to find the optimal phase and timing for CA signals. This includes finer granularity in delay adjustments, additional training steps, and more comprehensive window searches. This results in a more robust alignment of CA signals, reducing the risk of setup or hold violations.

CLK PUSH ORDER DURING TRAINING

This option determines the sequence in which clock (CK) signals are pushed during the DDR training process. Pushing the clock refers to incrementally shifting the clock phase or delay to find the optimal alignment between the clock and data/command/address signals. This option imapacts the following aspects of training:

- Training Sequence and Signal Alignment:
  - The order in which clock signals are pushed can affect how the controller searches for the best timing window for data and command/address sampling.
  - Different push orders may be used to optimize training for specific board layouts, memory devices, or signal integrity conditions.
- Lane-by-Lane or Grouped Training:
  - Some boards may have multiple clock lanes or groups (e.g., for multi-rank or multi-chip DDR configurations).
  - The push order determines whether clocks are adjusted lane-by-lane, all at once, or in a specific sequence.
  - This can impact the ability to find the optimal timing for each lane, especially if there is skew or variation between lanes.
- Training Robustness and Margins:
  - The correct push order can help maximize timing margins and ensure reliable training across all lanes.
  - An inappropriate push order may cause some lanes to fail training or result in marginal operation, especially on custom boards with non-uniform trace lengths.
- Training Time:
  - The push order can also affect the overall training time. Sequential lane training may take longer but provide more robust results, while grouped training may be faster but less precise.

CLK PUSH ORDER DURING TRAINING includes the following options:

0 Degree Push Order: The First, Second, and Third settings under 0 Degree Push Order specify the order in which the controller attempts 0° phase alignment during DDR training. This sequencing helps optimize training reliability and speed by prioritizing the most likely successful phase alignments for your board. The following table lists the scenarios in which these settings can be used.

Table 20-23. 0 Degree Push Order Settings
Setting	Functionality	When to Use
First	Try 0° phase alignment first	Reference boards, default bring-up
Second	Try 0° after the first phase option fails	Custom boards, fallback
Third	Try 0° as the last phase alignment attempt	Troubleshooting, exhaustive search

45 Degree Push Order: The First, Second, and Third settings under 45 Degree Push Order specify the order in which the controller attempts a 45° phase alignment during DDR training. This sequencing helps optimize training reliability and speed by prioritizing the most likely successful phase alignments for your board. The following table lists the scenarios in which these settings can be used.

Table 20-24. 45 Degree Push Order Settings
Setting	Functionality	When to Use
First	Try 45° phase alignment first	Custom boards, known SI advantage
Second	Try 45° after the first phase option fails	Reference boards, fallback
Third	Try 45° as the last phase alignment attempt	Troubleshooting, exhaustive search

90 Degree Push Order: The First, Second, and Third settings under 90 Degree Push Order specify the order in which the controller attempts a 90° phase alignment during DDR training. This sequencing helps optimize training reliability and speed by prioritizing the most likely successful phase alignments for your board. The following table lists the scenarios in which these settings can be used.

Table 20-25. 90 Degree Push Order Settings
Setting	Functionality	When to Use
First	Try 90° phase alignment first	Custom boards, known SI advantage
Second	Try 90° after the first phase option fails	Reference boards, fallback
Third	Try 90° as the last phase alignment attempt	Troubleshooting, exhaustive search