4.4.1 Checking IRS Connectivity Against a Parameter File

MSVT checks that all inter-region signals are specified as IRS statements in the msvt.param file, and that the specified IRS connections are consistent with the design netlist. A missing IRS net or invalid connection is counted as an error and listed in the Checking IRS connectivity against parameter file section.

The following example is a msvt.param file that has missing IRS signals.

VERIFY_BLOCKS = Block_Cdr_0 COretse_Block1_0 // empty list means all blocks in design will be verified
REQUIRED_SEPARATION = 2
MAX_VIOLATIONS_PER_REPORT_SECTION = 1
IRS Block_Cdr_0 COretse_Block1_0 = Block_Cdr_0_APBmslave0_PADDR[9] Block_Cdr_0_APBmslave0_PADDR[8]
        Block_Cdr_0_APBmslave0_PADDR[7] Block_Cdr_0_APBmslave0_PADDR[6] Block_Cdr_0_APBmslave0_PADDR[5]
        Block_Cdr_0_APBmslave0_PADDR[4] Block_Cdr_0_APBmslave0_PADDR[3] Block_Cdr_0_APBmslave0_PADDR[2]
        Block_Cdr_0_APBmslave0_PENABLE Block_Cdr_0_to_CORETSE_Preset Block_Cdr_0_APBmslave0_PSELx
        Block_Cdr_0_APBmslave1_PSELx Block_Cdr_0_APBmslave2_PSELx Block_Cdr_0_APBmslave0_PWDATA[31]
        Block_Cdr_0_APBmslave0_PWDATA[30] Block_Cdr_0_APBmslave0_PWDATA[29] Block_Cdr_0_APBmslave0_PWDATA[28]
        Block_Cdr_0_APBmslave0_PWDATA[27] Block_Cdr_0_APBmslave0_PWDATA[26] Block_Cdr_0_APBmslave0_PWDATA[25]
        Block_Cdr_0_APBmslave0_PWDATA[24] Block_Cdr_0_APBmslave0_PWDATA[23] Block_Cdr_0_APBmslave0_PWDATA[22]
        Block_Cdr_0_APBmslave0_PWDATA[21] Block_Cdr_0_APBmslave0_PWDATA[20] Block_Cdr_0_APBmslave0_PWDATA[19]
        Block_Cdr_0_APBmslave0_PWDATA[18] Block_Cdr_0_APBmslave0_PWDATA[17] Block_Cdr_0_APBmslave0_PWDATA[16]
        Block_Cdr_0_APBmslave0_PWDATA[15] Block_Cdr_0_APBmslave0_PWDATA[14] Block_Cdr_0_APBmslave0_PWDATA[13]
        Block_Cdr_0_APBmslave0_PWDATA[12] Block_Cdr_0_APBmslave0_PWDATA[11] Block_Cdr_0_APBmslave0_PWDATA[10]
        Block_Cdr_0_APBmslave0_PWDATA[9] Block_Cdr_0_APBmslave0_PWDATA[8] Block_Cdr_0_APBmslave0_PWDATA[7]
        Block_Cdr_0_APBmslave0_PWDATA[6] Block_Cdr_0_APBmslave0_PWDATA[5] Block_Cdr_0_APBmslave0_PWDATA[4]
        Block_Cdr_0_APBmslave0_PWDATA[3] Block_Cdr_0_APBmslave0_PWDATA[2] Block_Cdr_0_APBmslave0_PWDATA[1]
        Block_Cdr_0_APBmslave0_PWDATA[0] Block_Cdr_0_APBmslave0_PWRITE Block_Cdr_0_RX_DATA[9]
        Block_Cdr_0_RX_DATA[8] Block_Cdr_0_RX_DATA[7] Block_Cdr_0_RX_DATA[6] Block_Cdr_0_RX_DATA[5]
        Block_Cdr_0_RX_DATA[4] Block_Cdr_0_RX_DATA[3] Block_Cdr_0_RX_DATA[2] Block_Cdr_0_RX_DATA[1]
        Block_Cdr_0_RX_DATA[0] Block_Cdr_0_RX_CLK_R Block_Cdr_0/PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/N_1_inferred_clock_RNI51A9/U0_Y
IRS COretse_Block1_0 Block_Cdr_0 = Block_Cdr_0_APBmslave0_PRDATA[31] Block_Cdr_0_APBmslave0_PRDATA[30]
        Block_Cdr_0_APBmslave0_PRDATA[29] Block_Cdr_0_APBmslave0_PRDATA[28] Block_Cdr_0_APBmslave0_PRDATA[27]
        Block_Cdr_0_APBmslave0_PRDATA[26] Block_Cdr_0_APBmslave0_PRDATA[25] Block_Cdr_0_APBmslave0_PRDATA[24]
        Block_Cdr_0_APBmslave0_PRDATA[23] Block_Cdr_0_APBmslave0_PRDATA[22] Block_Cdr_0_APBmslave0_PRDATA[21]
        Block_Cdr_0_APBmslave0_PRDATA[20] Block_Cdr_0_APBmslave0_PRDATA[19] Block_Cdr_0_APBmslave0_PRDATA[18]
        Block_Cdr_0_APBmslave0_PRDATA[17] Block_Cdr_0_APBmslave0_PRDATA[16] Block_Cdr_0_APBmslave0_PRDATA[15]
        Block_Cdr_0_APBmslave0_PRDATA[14] Block_Cdr_0_APBmslave0_PRDATA[13] Block_Cdr_0_APBmslave0_PRDATA[12]
        Block_Cdr_0_APBmslave0_PRDATA[11] Block_Cdr_0_APBmslave0_PRDATA[10] Block_Cdr_0_APBmslave0_PRDATA[9]
        Block_Cdr_0_APBmslave0_PRDATA[8] Block_Cdr_0_APBmslave0_PRDATA[7] Block_Cdr_0_APBmslave0_PRDATA[6]
        Block_Cdr_0_APBmslave0_PRDATA[5] Block_Cdr_0_APBmslave0_PRDATA[4] Block_Cdr_0_APBmslave0_PRDATA[3]
        Block_Cdr_0_APBmslave0_PRDATA[2] Block_Cdr_0_APBmslave0_PRDATA[1] Block_Cdr_0_APBmslave0_PRDATA[0]
        Block_Cdr_0_APBmslave1_PRDATA[15] Block_Cdr_0_APBmslave1_PRDATA[14] Block_Cdr_0_APBmslave1_PRDATA[13]
        Block_Cdr_0_APBmslave1_PRDATA[12] Block_Cdr_0_APBmslave1_PRDATA[11] Block_Cdr_0_APBmslave1_PRDATA[10]
        Block_Cdr_0_APBmslave1_PRDATA[9] Block_Cdr_0_APBmslave1_PRDATA[8] Block_Cdr_0_APBmslave1_PRDATA[7]
        Block_Cdr_0_APBmslave1_PRDATA[6] Block_Cdr_0_APBmslave1_PRDATA[5] Block_Cdr_0_APBmslave1_PRDATA[4]
        Block_Cdr_0_APBmslave1_PRDATA[3] Block_Cdr_0_APBmslave1_PRDATA[2] Block_Cdr_0_APBmslave1_PRDATA[1]
        Block_Cdr_0_APBmslave1_PRDATA[0] Block_Cdr_0_APBmslave2_PRDATA[7] Block_Cdr_0_APBmslave2_PRDATA[6]
        Block_Cdr_0_APBmslave2_PRDATA[5] Block_Cdr_0_APBmslave2_PRDATA[4] Block_Cdr_0_APBmslave2_PRDATA[3]
        Block_Cdr_0_APBmslave2_PRDATA[2] Block_Cdr_0_APBmslave2_PRDATA[1] Block_Cdr_0_APBmslave2_PRDATA[0]
        COretse_Block1_0_TCG[9] COretse_Block1_0_TCG[8] COretse_Block1_0_TCG[7]
        COretse_Block1_0_TCG[6] COretse_Block1_0_TCG[5] COretse_Block1_0_TCG[4]
        COretse_Block1_0_TCG[3] COretse_Block1_0_TCG[2] COretse_Block1_0_TCG[1]
        COretse_Block1

The top-level design must contain only blocks, or at least very few other instances. The errors in this example are most likely caused by ‘others’ on top level. The nets connecting blocks to ‘others’ are IRS to the blocks, but not listed in the msvt.param file.

--------------------------------------------------------
Checking IRS connectivity against parameter file
===================================================
   Error: IRS net PHY_RST_c is not listed in param file
   Error: IRS net coma_mode_c is not listed in param file
   Error: IRS net LINK_OK_c is not listed in param file
   Error: IRS net PHY_RST_0_c is not listed in param file
   Error: IRS net RD_BC_ERROR_c is not listed in param file
   Error: IRS net SPISCLKO_c is not listed in param file
   Error: IRS net SPISDO_c is not listed in param file
   Error: IRS net SPISS_c is not listed in param file
   Error: IRS net TX_c is not listed in param file
   Error: IRS net coma_mode_0_c is not listed in param file
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