1.2.5.6.1 Abstraction Model

To understand how this library works you must first understand how an external Ethernet PHY interfaces with the Ethernet Controller. As shown in Figure 1, the PHY has two interfaces:

The management interface for configuration/control of the PHY, known as the Media Independent Interface Management (MIIM) or Serial Management Interface (SMI)

The transmit and receive data interface, which could be the Media Independent Interface (MIIM) or the Reduced Media Independent Interface (RMII)

The block diagram also shows an interrupt signal (nINT) going to an external interrupt pin on the host device and signals going to on-board LEDs to show link state and link activity.

The SMI or MIIM interface controls the PHY. This control interface is standardized for all PHYs by Clause 22 of the 802.3 standard. It provides up to 32 16-bit registers on the PHY. The following table provides a summary of all 32 registers. Consult the data sheet for the PHY device for the specific bit fields in each register.