21.9.5 TxCLKCON

Timer Clock Source Selection Register
Name: TxCLKCON
Address: 0xFBE,0xFB8,0xFB2

Bit 76543210 
     CS[3:0] 
Access R/WR/WR/WR/W 
Reset 0000 

Bits 3:0 – CS[3:0] Timer Clock Source Selection bits

Table 21-3. Clock Source Selection
CS[3:0]Clock Source
Timer2Timer4Timer6
1111-1001ReservedReservedReserved
1000ZCD_OUTZCD_OUTZCD_OUT
0111CLKREF_OUTCLKREF_OUTCLKREF_OUT
0110SOSCSOSCSOSC
0101MFINTOSC (31 kHz)MFINTOSC (31 kHz)MFINTOSC (31 kHz)
0100LFINTOSCLFINTOSCLFINTOSC
0011HFINTOSCHFINTOSCHFINTOSC
0010FoscFoscFosc
0001Fosc/4 Fosc/4 Fosc/4
0000Pin selected by T2INPPSPin selected by T4INPPSPin selected by T6INPPS
ValueDescription
nSee the “Clock Source Selection” table