9.11 Determining the Cause of a Reset

Upon any Reset, multiple bits in the STATUS and PCON0 registers are updated to indicate the cause of the Reset. The following table shows the Reset conditions of these registers.

Table 9-3. Reset Condition for Special Registers
Condition	Program Counter	STATUS Register^(2,3)	PCON0 Register	PCON1 Register
Power-on Reset	0	`-110 0000`	`0011 110x`	`---- -1-1`
Brown-out Reset	0	`-110 0000`	`0011 11u0`	`---- -u-u`
MCLR Reset during normal operation	0	`-uuu uuuu`	`uuuu 0uuu`	`uuuu-u-u`
MCLR Reset during Sleep	0	`-10u uuuu`	`uuuu 0uuu`	`uuuu-u-u`
WDT Time-out Reset	0	`-0uu uuuu`	`uuu0 uuuu`	`uuuu-u-u`
WDT Wake-up from Sleep	PC + 2	`-00u uuuu`	`uuuu uuuu`	`uuuu-u-u`
WWDT Window Violation Reset	0	`-uuu uuuu`	`uu0u uuuu`	`uuuu-u-u`
Interrupt Wake-up from Sleep	PC + 2⁽¹⁾	`-10u 0uuu`	`uuuu uuuu`	`uuuu-u-u`
`RESET` Instruction Executed	0	`-uuu uuuu`	`uuuu u0uu`	`uuuu-u-u`
Stack Overflow Reset (STVREN = `1`)	0	`-uuu uuuu`	`1uuu uuuu`	`uuuu-u-u`
Stack Underflow Reset (STVREN = `1`)	0	`-uuu uuuu`	`u1uu uuuu`	`uuuu-u-u`
Data Protection (Fuse Fault)	0	`---u uuuu`	`uuuu uuuu`	`---- -u-0`
VREG or ULP Ready Fault	0	`---1 1000`	`0011 001u`	`---- -0-1`

Legend: u = unchanged, x = unknown, — = unimplemented bit, reads as ‘0’.

Note:

When the wake-up is due to an interrupt and Global Interrupt Enable bit (GIE) is set, the return address is pushed on the stack and PC is loaded with the corresponding interrupt vector (depending on source, high or low priority) after execution of PC + 2.
If a Status bit is not implemented, that bit will be read as ‘0’.
Status bits Z, C, DC are reset by POR/BOR.