8.4.1 PMD0

PMD Control Register 0

Note:

Clearing the SYSCMD bit disables the system clock (F_OSC) to peripherals, however peripherals clocked by F_OSC/4 are not affected.
Subject to SCANE bit in Configuration Word 4.
When enabling NVM, a delay of up to 1 µs is required before accessing data.

Name:	PMD0
Address:	0xEDC


Bit	7	6	5	4	3	2	1	0
	SYSCMD	FVRMD	HLVDMD	CRCMD	SCANMD	NVMMD	CLKRMD	IOCMD
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bit 7 – SYSCMD Disable Peripheral System Clock Network bit

Disables the System clock network⁽¹⁾

Value	Description
1	System clock network disabled (F_OSC)
0	System clock network enabled

Bit 6 – FVRMD Disable Fixed Voltage Reference bit

Value	Description
1	FVR module disabled
0	FVR module enabled

Bit 5 – HLVDMD Disable High-Low-Voltage Detect bit

Value	Description
1	HLVD module disabled
0	HLVD module enabled

Bit 4 – CRCMD Disable CRC Engine bit

Value	Description
1	CRC module disabled
0	CRC module enabled

Bit 3 – SCANMD Disable NVM Memory Scanner bit

Disables the Scanner module⁽²⁾

Value	Description
1	NVM Memory Scan module disabled
0	NVM Memory Scan module enabled

Bit 2 – NVMMD NVM Module Disable bit

Disables the NVM module⁽³⁾

Value	Description
1	All Memory reading and writing is disabled; NVMCON registers cannot be written
0	NVM module enabled

Bit 1 – CLKRMD Disable Clock Reference bit

Value	Description
1	CLKR module disabled
0	CLKR module enabled

Bit 0 – IOCMD Disable Interrupt-on-Change bit, All Ports

Value	Description
1	IOC module(s) disabled
0	IOC module(s) enabled

Clearing the SYSCMD bit disables the system clock (FOSC) to peripherals, however peripherals clocked by FOSC/4 are not affected.Subject to SCANE bit in Configuration Word 4.When enabling NVM, a delay of up to 1 µs is required before accessing data.