25.15.9 CWGxSTR

CWG Steering Control Register⁽¹⁾

Note:

The bits in this register apply only when MODE = ‘00x’ (see CWGxCON0 and the “Steering Modes” section).
This bit is double-buffered when MODE = ‘001’.

Name:	CWGxSTR
Address:	0x0F43


Bit	7	6	5	4	3	2	1	0
	OVRD	OVRC	OVRB	OVRA	STRD	STRC	STRB	STRA
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 4, 5, 6, 7 – OVRy Steering Data OVR'y' bit

Value	Name	Description
`x`	STRy = `1`	CWGx'y' output has the CWG data input waveform with polarity control from the POLy bit
`1`	STRy = `0` and POLy = `x`	CWGx'y' output is high
`0`	STRy = `0` and POLy = `x`	CWGx'y' output is low

Bits 0, 1, 2, 3 – STRy STR'y' Steering Enable bit⁽²⁾

Value	Description
`1`	CWGx'y' output has the CWG data input waveform with polarity control from the POLy bit
`0`	CWGx'y' output is assigned to value of the OVRy bit

The bits in this register apply only when MODE = ‘00x’ (see CWGxCON0CWGxCON0 and the “Steering Modes” section).This bit is double-buffered when MODE = ‘001’.

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