10.8.5 WDTTMR

WDT Timer Register (Read-Only)

Note:

The 18-bit WDT prescale value, PSCNT[17:0], includes the WDTPSL, WDTPSH and the lower two bits of the WDTTMR registers. PSCNT[17:0] is intended for debug operations and may be read during normal operation.

Name:	WDTTMR
Address:	0xED1


Bit	7	6	5	4	3	2	1	0
	WDTTMR[4:0]					STATE	PSCNT[1:0]
Access	RO	RO	RO	RO	RO	RO	RO	RO
Reset	0	0	0	0	0	0	0	0

Bits 7:3 – WDTTMR[4:0] Watchdog Window Value bits


WINDOW	WDT Window State		Open Percent
WINDOW	Closed	Open	Open Percent
`111`	N/A	`00000-11111`	100
`110`	`00000-00011`	`00100-11111`	87.5
`101`	`00000-00111`	`01000-11111`	75
`100`	`00000-01011`	`01100-11111`	62.5
`011`	`00000-01111`	`10000-11111`	50
`010`	`00000-10011`	`10100-11111`	37.5
`001`	`00000-10111`	`11000-11111`	25
`000`	`00000-11011`	`11100-11111`	12.5

Bit 2 – STATE WDT Armed Status bit

Value	Description
`1`	WDT is armed
`0`	WDT is not armed

Bits 1:0 – PSCNT[1:0] Prescale Select Upper bits⁽¹⁾

The 18-bit WDT prescale value, PSCNT[17:0], includes the WDTPSL, WDTPSH and the lower two bits of the WDTTMR registers. PSCNT[17:0] is intended for debug operations and may be read during normal operation.

10.8.5 WDTTMR

Bits 7:3 – WDTTMR[4:0] Watchdog Window Value bits

Bit 2 – STATE WDT Armed Status bit

Bits 1:0 – PSCNT[1:0] Prescale Select Upper bits(1)

Bits 1:0 – PSCNT[1:0] Prescale Select Upper bits⁽¹⁾