32.7.5 ADSTAT

ADC Status Register

Note:

If ADCS = 1, and F_OSC < F_RC, the indicated status may not be valid.
If ADC clock source is ADCRC and F_OSC < ADRC, the indicated status may not be valid.
STAT = 'b100 appears between the two triggers when DSEN = 1 and CONT = 0.

Name:	ADSTAT
Address:	0xF60


Bit	7	6	5	4	3	2	1	0
	ADAOV	ADUTHR	ADLTHR	ADMATH		ADSTAT[2:0]
Access	R/C/HS/HC	RO	RO	R/C/HS/HC		RO	RO	RO
Reset	0	0	0	0		0	0	0

Bit 7 – ADAOV ADC Accumulator Overflow bit

Value	Description
1	ADC accumulator or ADERR calculation have overflowed
0	ADC accumulator and ADERR calculation have not overflowed

Bit 6 – ADUTHR ADC Module Greater-than Upper Threshold Flag bit

Value	Description
1	ADERR > ADUTH
0	ADERR ≤ ADUTH

Bit 5 – ADLTHR ADC Module Less-than Lower Threshold Flag bit

Value	Description
1	ADERR < ADLTH
0	ADERR ≥ ADLTH

Bit 4 – ADMATH ADC Module Computation Status bit

Value	Description
1	Registers ADACC, ADFLTR, ADUTH, ADLTH and the ADAOV bit are updating or have already updated
0	Associated registers/bits have not changed since this bit was last cleared

Bits 2:0 – ADSTAT[2:0]

ADC Module Cycle Multi-Stage Status bits⁽¹⁾

Value	Description
111	ADC module is in 2^nd conversion stage
110	ADC module is in 2^nd acquisition stage
101	ADC module is in 2^nd precharge stage
100	ADC computation is suspended between 1^st and 2^nd sample; the computation results are incomplete and awaiting data from the 2^nd sample ^(2,3)
011	ADC module is in 1^st conversion stage
010	ADC module is in 1^st acquisition stage
001	ADC module is in 1^st precharge stage
000	ADC module is not converting

If ADCS = 1, and FOSC < FRC, the indicated status may not be valid. If ADC clock source is ADCRC and FOSC < ADRC, the indicated status may not be valid. STAT = 'b100 appears between the two triggers when DSEN = 1 and CONT = 0.