10 Appendix B: MPLAB® Code Configuration (MCC) Peripheral Configuration

In this section, the initialization and configuration of the peripherals utilized in this application note using MPLAB® Code Configurator (MCC) are shown. MCC is a plug-in tool of MPLAB® X IDE, which provides a graphical environment where peripheral configuration can be executed. MCC generates drivers in C code, which initializes the peripherals and provides functions that can be called on your firmware. Refer to the MPLAB® Code Configurator V3.xx User's Guide (DS40001829) for more information on how to install and set up the MCC in MPLAB X IDE.

The following steps provide the MCC settings of each PIC18-Q43 peripheral used in this application note.
  1. Select HFINTOSC as the clock source with a 64 MHz frequency in the system module.
  2. For the Motor Angular Position, TMR4, CLC1, TMR3 CCP1 and TMR1 are configured. The clock source of TMR4 is set to FOSC/4. To provide 192 interrupts in a Hall period, set the TMR4 period to 12.0625 µs according to Equation 3-2.
  3. Using the CLC1 module, the TMR4 input is redirected to TMR3 input. In the AND-OR mode of CLC1, TMR4 output is selected as input to two OR gates. This configuration acts as a buffer logic that provides input to TMR3 clock.
  4. The output of CLC1 is used as an input of TMR3. Every time the TMR4 output is set, TMR3 is incremented by one. It is done to count the number of TMR4 period in a Hall period. Each time a Hall period is detected, the TMR3 counter register is copied to the compare register of CCP and then reloaded with the initial value.
  5. Set the CCP1 module to Compare mode. Select the TMR1 module as the timer in which the compare register value is always compared. Select pulse clear timer as the Compare operating mode. Enable the CCP interrupt to provide an ISR that will reload TMR1 every matching event.
  6. Select FOSC/4 as the TMR1 clock source to perform hardware division with TMR4.
  7. The drive signal generator requires that the DMA controller, PWM and CWG modules to be configured. For the PWM module, a single slice is used for each bridge. Select HFINTOSC as the clock source for each PWM module without a prescale value. Choose the Center-aligned mode as the operating mode. Set the requested frequency to 40 kHz, to provide a 10-bit resolution for the duty cycle. In the register’s tab, set the PWMxLDS to the corresponding DMA channel to automatically reload the duty cycle value to the PWM output every time the DMA successfully transmitts an element.
  8. Disable the CWG module, since the motor is initialized in a Stop condition. Set the PWMxOUT1 register as the input source for the operation. Steering mode is selected as the Output mode since the motor starts in the trapezoidal drive, but changes to the Half-Bridge mode during firmware execution, if motor speed is established. The dead-band count for falling and rising events are set to 63-64 counts with the HFINTOSC clock source.
  9. The DMA controller channels are initially disabled and will be manually enabled in the firmware. Set the DMODE and SMODE bits in the DMAxCON1 register to “incremented”. Select the program Flash memory as the source in the DMAxCON1 register. For the DMA source address, enter the address location of the corresponding PWM slice register. In MPLAB® X IDE, the address of the register can be easily identified by clicking Window > Target Memory Views > SFR. An SFR tab will pop up showing a list of registers and their addressess. Set the DMAxDSZ register to 2, since the PWM duty cycle register has a 2-byte size. For the source address size, set 0x40 to the DMAxSSZ register. CCP1 is selected as an interrupt request source in the DMAxSIRQ register.
  10. For the Fault detection feature, TMR0 is used to insert a delay before enabling Fault detection. Set the clock Prescaler to 1:32 and the Postscaler to 1:10. Set the clock source to LFINTOSC. Set the requested period to the desired delay sequence, before enabling the Fault detection features, which is 500 milliseconds. TMR0 is initialized as disabled, since the time set will start upon the motor running state.
  11. Set the DAC output value to 2.5V. For the positive and negative reference, choose VDD and VSS, respectively. Disable the DAC output in the DACOUT1 register. The positive input of the CMP module uses the DACOUT1 as the reference voltage. Choose the CIN2- as the negative input of the CMP module. Select the inverted output polarity to provide an output high when the negative input is greater than the DACOUT value. Using TMR6, the comparator output is checked every 50 ms. If the CMP output state is high, a trigger will stop the motor. To apply this scheme, enable the TMR6 interrupt and select LFINTOSC as the clock source. Change the Prescaler value of TMR6 to 1:64 and set the timer period to 50 ms.
  12. For stall detection, TMR2’s HLT mode is used. Choose the T2CKIPPS pin as the external Reset source to use the Hall B signal to detect a Stall condition. Choose “resets at rising TMR2_ers” as a Start/Reset option to reset the timer every time the Hall signal is detected before the TMR2 flag is set. For the TMR2 period, indicate the time in which, if no Hall signal is detected, it will trigger an interrupt. Enable TMR2 interrupt.
  13. Configure the output and input pins for the peripherals as shown in Figure 10-1.
Figure 10-1. Pin Manager and Pin Module Configuration

After setting all peripherals needed, click the “Generate code” in the resource management tab. It will generate peripheral drivers and a main.c, where all peripherals are initialized based on your configuration.