5.6.1 Implicit Alignment in Program Memory

In addition to directives that explicitly align the location counter (such as .align, .palign, .org, .porg, etc.), many statements cause an implicit alignment to occur under certain conditions. Implicit alignment occurs when padding is inserted so that the next statement begins at a valid address. Padding uses the current .fillvalue and .fillupper values if specified; otherwise the value zero is used.

In data memory, a valid address is available for each byte. Since no data directives specify memory in quantities of less than one byte, implicit alignment is not required in data memory.

In program memory, a valid address is available for each instruction word (3 or 4 bytes). Since data directives can specify individual bytes, implicit alignment to the next valid address is sometimes required.

The following conditions cause implicit alignment in program memory:

Labels must be aligned to a valid address. For example, see the following source code:
```
   .text
   .pbyte 0x11
L1:
   .pbyte 0x22
   .pbyte 0x33,0x44
```
This generates implicit alignment as shown in the disassembly of section .text:
```
00000000 <.text>:
   0: 11 00 00 nop
00000002 <L1>:
   2: 22 33 44 .pword 0x443322
```
Note: Two bytes of padding were inserted so that label L1 would be aligned to a valid address.
On dsPIC33A architectures, three bytes of padding are inserted so that label L1 would be aligned to a valid address. In this example, the dis-assembler has interpreted the data bytes as a sequence of 16-bit opcodes. Keep in mind that a valid instruction address must be divisible by four, even though the instruction word may contain two 16-bit opcodes.
```
00000000 <L1-0x4>:
   0:	11 00       	neop      
   2:	00 00       	neop      

00000004 <L1>:
   4:	22 33       	rlnc.l    w2, w2
   6:	44 00       	neop
```
Instructions must be aligned to a valid address. For example, see the following source code:
```
.text
.pbyte 0x11
 mov w2,w3
```
This generates implicit alignment as shown in the disassembly of section .text:
```
00000000 <.text>:
   0: 11 00 00 nop 
   2: 82 01 78 mov.w w2, w3
```
Note: Two bytes of padding were inserted so that the mov instruction would be aligned to a valid address.
On dsPIC33A architectures, three bytes of padding are inserted so that the mov w2,w3 instruction is aligned to a valid address.
```
00000000 <.text>:
   0:	11 00       	neop      
   2:	00 00       	neop      
   4:	32 02       	mov.w     w2, w3
   6:	00 00       	neop      
```
Transitions between p-type data directives (.pbyte, .pspace, etc). and normal data directives (.byte, .space, etc.), in either direction, are aligned to a valid address. For example, see the following source code:
```
.text
.byte 0x11
.pbyte 0x22
.pbyte 0x33,0x44
```
This generates implicit alignment as shown in the disassembly of section .text:
```
00000000 <.text>:
   0: 11 00 00 nop 
   2: 22 33 44 .pword 0x443322
```
Note: Two bytes of padding were inserted so that the transition from normal to p-type directive would be aligned to a valid address.
On dsPIC33A architectures, three bytes of padding are inserted so that the transition is aligned to a valid address.
```
00000000 <.text>:
   0:	11 00       	neop      
   2:	00 00       	neop      
   4:	22 33       	rlnc.l    w2, w2
   6:	44 00       	neop      
```