3 Pin Allocation Tables

Table 3-1. 40/44/48-Pin Allocation Table
I/O⁽²⁾	40- Pin PDIP	40- Pin QFN	44- Pin TQFP	48- Pin TQFP/ VQFN	A/D	Reference	Operational Amplifier	Comparator	ZCD/Analog Peripheral Manager	Timers	16-Bit PWM/ CCP	CWG	CLC	SPI	I²C	UART	IOC	Interrupt	Basic
RA0	2	17	19	21	ANA0	—	OPA1OR⁽¹⁾	C1IN0- C2IN0-	—	—	—	—	CLCIN0⁽¹⁾ CLCIN4⁽¹⁾	—	—	—	IOCA0	—	—
RA1	3	18	20	22	ANA1⁽⁶⁾	—	OPA1OUT OPA2IN1- OPA2IN1+	C1IN1- C2IN1-	—	—	—	—	CLCIN1⁽¹⁾ CLCIN5⁽¹⁾	—	—	—	IOCA1	—	—
RA2	4	19	21	23	ANA2	DAC1OUT1 DAC2OUT1 DAC3OUT1 V_REF- (DAC1) V_REF- (ADC)	OPA1IN0- OPA1IN0+	C1IN0+ C2IN0+	—	—	—	—	—	—	—	—	IOCA2	—	—
RA3	5	20	22	24	ANA3⁽⁶⁾	V_REF+ (DAC1) V_REF+ (ADC)	—	C1IN1+	—	—	—	—	—	—	—	—	IOCA3	—	—
RA4	6	21	23	25	ANA4	—	OPA1IN1- OPA1IN1+	—	—	T0CKI⁽¹⁾	—	—	—	—	—	—	IOCA4	—	—
RA5	7	22	24	26	ANA5⁽⁶⁾	—	OPA1IN2- OPA1IN2+	—	—	—	—	—	—	SS1⁽¹⁾	—	—	IOCA5	—	—
RA6	14	29	31	33	ANA6⁽⁶⁾	—	—	—	—	—	—	—	—	—	—	—	IOCA6	—	CLKOUT OSC2
RA7	13	28	30	32	ANA7⁽⁶⁾	—	—	—	—	—	—	—	—	—	—	—	IOCA7	—	OSC1 CLKIN
RB0	33	8	8	8	ANB0⁽⁶⁾	V_REF+ (DAC2)	—	C2IN1+	ZCDIN	—	—	CWG1⁽¹⁾	—	—	—	—	IOCB0	INT0⁽¹⁾	—
RB1	34	9	9	9	ANB1	—	OPA2OUT OPA1IN3- OPA1IN3+	C2IN3- C1IN3-	—	—	—	—	—	—	—⁽⁴⁾	—	IOCB1	INT1⁽¹⁾	—
RB2	35	10	10	10	ANB2⁽⁶⁾	—	OPA2IN3- OPA2IN3+	—	—	—	—	—	—	—	—⁽⁴⁾	—	IOCB2	INT2⁽¹⁾	—
RB3	36	11	11	11	ANB3	—	OPA2IN2- OPA2IN2+	C1IN2- C2IN2-	—	—	—	—	—	—	—	—	IOCB3	—	—
RB4	37	12	14	16	ANB4⁽⁶⁾ ADACT⁽¹⁾	—	OPA2IN0- OPA2IN0+	—	—	—	—	—	—	—	—	—	IOCB4	—	—
RB5	38	13	15	17	ANB5	V_REF- (DAC2)	—	—	—	T1G⁽¹⁾ TUIN1⁽¹⁾	—	—	—	—	—	—	IOCB5	—	—
RB6	39	14	16	18	ANB6⁽⁶⁾	—	—	—	—	—	—	—	CLCIN2⁽¹⁾ CLCIN6⁽¹⁾		—	CTS2⁽¹⁾	IOCB6	—	ICSPCLK
RB7	40	15	17	19	ANB7	DAC1OUT2 DAC2OUT2 DAC3OUT2	—	—	—	—	PWM3ERS⁽¹⁾	—	CLCIN3⁽¹⁾ CLCIN7⁽¹⁾	—	—	RX2⁽¹⁾	IOCB7	—	ICSPDAT
RC0	15	30	32	34	ANC0	—	—	—	—	T1CKI⁽¹⁾ T3CKI⁽¹⁾ T3G⁽¹⁾ TUIN0⁽¹⁾	—	—	—	—	—	—	IOCC0	—	SOSCO
RC1	16	31	35	35	ANC1⁽⁶⁾	—	—	—	—	—	CCP2⁽¹⁾	—	—	—	—	—	IOCC1	—	SOSCI
RC2	17	32	36	40	ANC2	V_REF+ (DAC3)	—	—	—	—	PWMIN0⁽¹⁾ CCP1⁽¹⁾	—	—	—	—	—	IOCC2	—	—
RC3	18	33	37	41	ANC3⁽⁶⁾	—	—	—	—	T2IN⁽¹⁾	PWM1ERS⁽¹⁾	—	—	SCK1⁽¹⁾	SCL1^(3,4)	—	IOCC3	—	—
RC4	23	38	42	46	ANC4	—	—	—	APMCLK	—	—	—	—	SDI1⁽¹⁾	SDA^(3,4)	—	IOCC4	—	—
RC5	24	39	43	47	ANC5	V_REF- (DAC3)	—	—	—	T4IN⁽¹⁾	PWM2ERS⁽¹⁾	—	—	—	—	—	IOCC5	—	—
RC6	25	40	44	48	ANC6⁽⁶⁾	—	OPA2OR⁽¹⁾	—	—	—	PWMIN1⁽¹⁾	—	—	—	—	CTS1⁽¹⁾	IOCC6	—	—
RC7	26	1	1	1	ANC7	—	—	—	—	—	—	—	—	—	—	RX1⁽¹⁾	IOCC7	—	—
RD0	19	34	38	42	AND0	—	—	—	—	—	—	—	—	—	—	—	—	—	—
RD1	20	35	39	43	AND1	—	—	—	—	—	—	—	—	—	—	—	—	—	—
RD2	21	36	40	44	AND2⁽⁶⁾	—	—	—	—	—	—	—	—	—	—	—	—	—	—
RD3	22	37	41	45	AND3⁽⁶⁾	—	—	—	—	—	—	—	—	—	—	—	—	—	—
RD4	27	2	2	2	AND4	—	—	—	—	—	—	—	—	—	—	—	—	—	—
RD5	28	3	3	3	AND5⁽⁶⁾	—	—	—	—	—	—	—	—	—	—	—	—	—	—
RD6	29	4	4	4	AND6	—	—	—	—	—	—	—	—	—	—	—	—	—	—
RD7	30	5	5	5	AND7⁽⁶⁾	—	—	—	—	—	—	—	—	—	—	—	—	—	—
RE0	8	23	25	27	ANE0	—	—	—	—	—	—	—	—	—	—	—	—	—	—
RE1	9	24	26	28	ANE1⁽⁶⁾	—	—	—	—	—	—	—	—	—	—	—	—	—	—
RE2	10	25	27	29	ANE2	—	—	—	—	—	—	—	—	—	—	—	—	—	—
RE3	1	16	18	20	—	—	—	—	—	—	—	—	—	—	—	—	IOCE3	—	V_PP/MCLR
RF0	—	—	—	36	ANF0	—	—	—	—	—	—	—	—	—	—	—	—	—	—
RF1	—	—	—	37	ANF1⁽⁶⁾	—	—	—	—	—	—	—	—	—	—	—	—	—	—
RF2	—	—	—	38	ANF2	—	—	—	—	—	—	—	—	—	—	—	—	—
RF3	—	—	—	39	ANF3⁽⁶⁾	—	—	—	—	—	—	—	—	—	—	—	—	—
RF4	—	—	—	12	ANF4⁽⁶⁾	—	—	—	—	—	—	—	—	—	—	—	—	—
RF5	—	—	—	13	ANF5	—	—	—	—	—	—	—	—	—	—	—	—	—
RF6	—	—	—	14	ANF6⁽⁶⁾	—	—	—	—	—	—	—	—	—	—	—	—	—
RF7	—	—	—	15	ANF7	—	—	—	—	—	—	—	—	—	—	—	—	—
V_SS	12, 31	6, 27	6, 29	6,31	—	—	—	—	—	—	—	—	—	—	—	—	—	—	V_SS
V_DD⁽⁵⁾	11, 32	7, 26	7, 28	7, 30	—	—	—	—	—	—	—	—	—	—	—	—	—	—	V_DD⁽⁵⁾
OUT⁽²⁾					ADGRDA ADGRDB	—	—	C1OUT C2OUT	—	TMR0	PWM11 PWM12 PWM21 PWM22 PWM31 PWM32 CCP1 CCP2	CWG1A CWG1B CWG1C CWG1D	CLC1OUT CLC2OUT CLC3OUT CLC4OUT CLC5OUT CLC6OUT CLC7OUT CLC8OUT	SS1 SCK1 SDO1	SDA1 SCL1	DTR1 RTS1 TX1 DTR2 RTS2 TX2	—	—	—
Note: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. Refer to the peripheral input selection table for details on which PORT pins may be used for this signal. All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options as described in the peripheral output selection table. This is a bidirectional signal. For normal module operation, the firmware may map this signal to the same pin in both the PPS input and PPS output registers. These pins are configured for I²C logic levels; The SCLx/SDAx signals may be assigned to any of these pins. PPS assignments to the other pins (e.g., RB1) will operate, but input logic levels will be standard LVBU/ST as selected by the INLVL register, instead of the I²C specific or SMBus input buffer thresholds. A 0.1 μF bypass capacitor to V_SS is required on all V_DD pins. This pin can be used as either a positive or negative analog input channel to the ADC.