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Ultra-Low Power Arm® ARM926EJ-S™ Processor-Based MPU, 600 MHz, Camera, LCD, 2D Graphics, Dual 10/100 Ethernet, CAN, USB, QSPI, FLEXCOMs, AES, SHA
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SAM9X60
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4
System Controller
4.3
Advanced Interrupt Controller (AIC)
4.3.8
Functional Description
4.3.8.1
Interrupt Source Control
Introduction
Reference Document
1
Overview
2
CPU and Interconnect
3
Memories
4
System Controller
4.1
Overview
4.2
System Controller Write Protection (SYSCWP)
4.3
Advanced Interrupt Controller (AIC)
4.3.1
Description
4.3.2
Embedded Characteristics
4.3.3
Block Diagram
4.3.4
Application Block Diagram
4.3.5
Detailed Block Diagram
4.3.6
I/O Line Description
4.3.7
Product Dependencies
4.3.8
Functional Description
4.3.8.1
Interrupt Source Control
4.3.8.1.1
Interrupt Source Mode
4.3.8.1.2
Interrupt Source Enabling
4.3.8.1.3
Interrupt Clearing and Setting
4.3.8.1.4
Interrupt Status
4.3.8.1.5
Internal Interrupt Source Input Stage
4.3.8.1.6
External Interrupt Source Input Stage
4.3.8.2
Interrupt Latencies
4.3.8.3
Normal Interrupt
4.3.8.4
Fast Interrupt
4.3.8.5
Protect Mode
4.3.8.6
Spurious Interrupt
4.3.8.7
General Interrupt Mask
4.3.8.8
Register Write Protection
4.3.9
Register Summary
4.4
General Purpose Backup Registers (GPBR)
4.5
Watchdog Timer (WDT)
4.6
Reset Controller (RSTC)
4.7
Real-Time Timer (RTT)
4.8
Real-Time Clock (RTC)
4.9
Shutdown Controller (SHDWC)
4.10
Periodic Interval Timer (PIT)
4.11
64-bit Periodic Interval Timer (PIT64B)
4.12
Debug Unit (DBGU)
4.13
Special Function Registers (SFR)
4.14
Slow Clock Controller (SCKC)
4.15
Clock Generator
4.16
Power Management Controller (PMC)
4.17
Parallel Input/Output Controller (PIO)
5
Image Subsystem
6
Audio Subsystem
7
Security and Cryptography Subsystem
8
Connectivity Subsystem
9
USB Subsystem
10
Electrical and Mechanical Characteristics
11
Revision History
Microchip Information
4.3.8.1 Interrupt Source Control
