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Ultra-Low Power Arm® ARM926EJ-S™ Processor-Based MPU, 600 MHz, Camera, LCD, 2D Graphics, Dual 10/100 Ethernet, CAN, USB, QSPI, FLEXCOMs, AES, SHA
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SAM9X60
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3
Memories
3.4
Programmable Multibit Error Correction Code Controller (PMECC)
3.4.3
Block Diagram
Introduction
Reference Document
1
Overview
2
CPU and Interconnect
3
Memories
3.1
Overview
3.2
External Bus Interface (EBI)
3.3
Static Memory Controller (SMC)
3.4
Programmable Multibit Error Correction Code Controller (PMECC)
3.4.1
Description
3.4.2
Embedded Characteristics
3.4.3
Block Diagram
3.4.4
Functional Description
3.4.5
Software Implementation
3.4.6
Register Summary
3.5
Programmable Multibit ECC Error Location Controller (PMERRLOC)
3.6
DDR-SDRAM Controller (MPDDRC)
3.7
SDRAM Controller (SDRAMC)
3.8
OTP Memory Controller (OTPC)
4
System Controller
5
Image Subsystem
6
Audio Subsystem
7
Security and Cryptography Subsystem
8
Connectivity Subsystem
9
USB Subsystem
10
Electrical and Mechanical Characteristics
11
Revision History
Microchip Information
3.4.3 Block Diagram
Figure 3-45.
PMECC Block Diagram
