To avoid data collisions, the SPI peripheral can be configured in buffered mode
by writing a '1' to the Buffer Mode Enable bit in the Control B register (BUFEN in
SPIn.CTRLB). In this mode, the SPI has additional interrupt flags and extra buffers. The
extra buffers are shown in Figure 26-1. There are two different modes for the Buffer mode,
selected with the Buffer mode Wait for Receive bit (BUFWR). The two different modes are
described below with timing diagrams.
Figure 26-3. SPI Timing Diagram in Buffer Mode
with BUFWR in SPIn.CTRLB Set to Zero
All writes to the Data register goes to the Transmit Buffer register. The figure
above shows that the value 0x43 is written to the Data register, but it is not immediately
transferred to the shift register so the first byte sent will be a dummy byte. The value of
the dummy byte is whatever was in the shift register at the time, usually the last received
byte. After the first dummy transfer is completed the value 0x43 is transferred to the
Shift register. Then 0x44 is written to the Data register and goes to the Transmit Buffer
register. A new transfer is started and 0x43 will be sent. The value 0x45 is written to the
Data register, but the Transmit Buffer register is not updated since it is already full
containing 0x44 and the Data Register Empty Interrupt Flag (DREIF in SPIn.INTFLAGS) is low.
The value 0x45 will be lost. After the transfer, the value 0x44 is moved to the Shift
register. During the next transfer, 0x46 is written to the Data register and 0x44 is sent
out. After the transfer is complete 0x46 is copied into the Shift register and sent out in
the next transfer.
The Data Register Empty Interrupt Flag (DREIF in SPIn.INTFLAGS) goes low every
time the Transmit Buffer register is written and goes high after a transfer when the
previous value in the Transmit Buffer register is copied into the Shift register. The
Receive Complete Interrupt Flag (RXCIF in SPIn.INTFLAGS) is set one cycle after the Data
Register Empty Interrupt Flag goes high. The Transfer Complete Interrupt Flag is set one
cycle after the Receive Complete Interrupt Flag is set when both the value in the shift
register and the Transmit Buffer register have been sent.
Figure 26-4. SPI Timing Diagram in Buffer Mode
with CTRLB.BUFWR Set to One
All writes to the Data register goes to the transmit buffer. The figure above shows
that the value 0x43 is written to the Data register and since the Slave Select pin is high
it is copied to the Shift register the next cycle. Then the next write (0x44) will go to
the Transmit Buffer register. During the first transfer, the value 0x43 will be shifted
out. In the figure, the value 0x45 is written to the Data register, but the Transmit Buffer
register is not updated since the Data Register Empty Interrupt Flag is low. After the
transfer is completed the value 0x44 from the Transmit Buffer register is copied over to
the Shift register. The value 0x46 is written to the Transmit Buffer register. During the
next two transfers, 0x44 and 0x46 are shifted out. The flags behave the same as with Buffer
mode Wait for Receive Bit (BUFWR in SPIn.CTRLB) set to zero.
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