25.1 Features

  • Full-Duplex or One-Wire Half-Duplex Operation
  • Asynchronous or Synchronous Operation:
    • Synchronous clock rates up to 1/2 of the device clock frequency
    • Asynchronous clock rates up to 1/8 of the device clock frequency
  • Supports Serial Frames with:
    • 5, 6, 7, 8, or 9 data bits
    • Optionally even and odd parity bits
    • 1 or 2 Stop bits
  • Fractional Baud Rate Generator:
    • Can generate desired baud rate from any system clock frequency
    • No need for external oscillator with certain frequencies
  • Built-In Error Detection and Correction Schemes:
    • Odd or even parity generation and parity check
    • Data overrun and framing error detection
    • Noise filtering includes false Start bit detection and digital low-pass filter
  • Separate Interrupts for:
    • Transmit complete
    • Transmit Data register empty
    • Receive complete
  • Multiprocessor Communication mode:
    • Addressing scheme to address specific devices on a multi-device bus
    • Enable unaddressed devices to automatically ignore all frames
  • Start Frame Detection in UART mode
  • Master SPI mode:
    • Double buffered operation
    • Configurable data order
    • Operation up to 1/2 of the peripheral clock frequency
  • IRCOM Module for IrDA Compliant Pulse Modulation/Demodulation
  • LIN Slave Support:
    • Auto-baud and Break character detection
  • RS-485 Support