3 Pin Allocation Tables

Table 3-1. 28-Pin Allocation Table
I/O(2) 28-

Pin

SPDIP,

SOIC,

SSOP

28-

Pin

VQFN

A/D Reference Comparator ZCD Timers/SMT 16-Bit PWM/

CCP

CWG CLC SPI I2C UART DSM IOC Interrupt CAN FD CRC on Boot JTAG Basic

RA0

2

27

ANA0

C1IN0-

C2IN0-

CLCIN0(1)

CLCIN4(1)

IOCA0

TMS

RA1

3

28

ANA1

C1IN1-

C2IN1-

CLCIN1(1)

CLCIN5(1)

IOCA1

RA2

4

1

ANA2

DAC1OUT1

VREF- (DAC)

VREF- (ADC)

C1IN0+

C2IN0+

IOCA2

BOOTA2

RA3

5

2

ANA3

VREF+ (DAC)

VREF+ (ADC)

C1IN1+

MDCARL(1)

IOCA3

RA4

6

3

ANA4 T0CKI(1) SS2(1) CTS5(1)

MDCARH(1)

IOCA4

BOOTA4

RA5

7

4

ANA5

SS1(1) RX5(1)

MDSRC(1)

IOCA5

TCK

RA6

10

7

ANA6

CTS3(1)

IOCA6

CLKOUT

OSC2

RA7

9

6

ANA7

RX3(1)

IOCA7

OSC1

CLKIN

RB0

21

18

ANB0

C2IN1+

ZCDIN

CWG1(1)

IOCB0

INT0(1)

RB1 22 19 ANB1

C1IN3-

C2IN3-

CWG2(1)

(4)

IOCB1

INT1(1)

RB2 23 20 ANB2

CWG3(1)

SDI2(1) (4)

IOCB2

INT2(1)

RB3 24 21 ANB3

C1IN2-

C2IN2-

SCK2(1) IOCB3 CANRX(1) TDO
RB4 25 22

ANB4

ADACT(1)

T5G(1) CTS4(1) IOCB4
RB5 26 23 ANB5 T1G(1) CCP3(1) RX4(1) IOCB5 TDI
RB6 27 24 ANB6

CLCIN2(1)

CLCIN6(1)

CTS2(1) IOCB6 ICSPCLK
RB7 28 25 ANB7 DAC1OUT2 T6IN(1) PWM3ERS(1)

CLCIN3(1)

CLCIN7(1)

RX2(1) IOCB7 ICSPDAT
RC0 11 8 ANC0

T1CKI(1)

T3CKI(1)

T3G(1)

SMT1WIN(1)

IOCC0 SOSCO
RC1 12 9 ANC1 SMT1SIG(1) CCP2(1) IOCC1 SOSCIN

SOSCI

RC2 13 10 ANC2 T5CKI(1)

PWMIN0(1)

CCP1(1)

IOCC2
RC3 14 11 ANC3 T2IN(1) PWM1ERS(1) SCK1(1) SCL1(3,4) IOCC3
RC4 15 12 ANC4 SDI1(1) SDA(3,4) IOCC4 BOOTC4
RC5 16 13 ANC5 T4IN(1) PWM2ERS(1) IOCC5 BOOTC5
RC6 17 14 ANC6 PWMIN1(1) CTS1(1) IOCC6
RC7 18 15 ANC7 RX1(1) IOCC7
RE3 1 26 IOCE3 Vpp/MCLR
VSS 19 16 VSS
VDD(5) 20 17 VDD(5)
VSS 8 5 VSS
OUT(2)

ADGRDA

ADGRDB

C1OUT

C2OUT

TMR0

PWM11

PWM12

PWM21

PWM22

PWM31

PWM32

CCP1

CCP2

CCP3

CWG1A

CWG1B

CWG1C

CWG1D

CWG2A

CWG2B

CWG2C

CWG2D

CWG3A

CWG3B

CWG3C

CWG3D

CLC1OUT

CLC2OUT

CLC3OUT

CLC4OUT

CLC5OUT

CLC6OUT

CLC7OUT

CLC8OUT

SS1

SCK1

SDO1

SS2

SCK2

SDO2

SDA1

SCL1

DTR1

RTS1

TX1

DTR2

RTS2

TX2

DTR3

RTS3

TX3

DTR4

RTS4

TX4

DTR5

RTS5

TX5

DSM1 CANTX
Note:
  1. This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. Refer to the peripheral input selection table for details on which PORT pins may be used for this signal.
  2. All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options as described in the peripheral output selection table.
  3. This is a bidirectional signal. For normal module operation, the firmware needs to map this signal to the same pin in both the PPS input and PPS output registers.
  4. These pins are configured for I2C logic levels; The SCLx/SDAx signals may be assigned to any of these pins. PPS assignments to the other pins (e.g., RB1) will operate, but input logic levels will be standard TTL/ST as selected by the INLVL register, instead of the I2C specific or SMBus input buffer thresholds.
  5. A 0.1 uF bypass capacitor to VSS is required on the VDD pin.
Table 3-2.  40/44/48-Pin Allocation Table
I/O(2) 40-

Pin

PDIP

40-

Pin

VQFN

44-

Pin

TQFP

48-

Pin

TQFP /

VQFN

A/D Reference Comparator ZCD Timers/SMT 16-Bit PWM/

CCP

CWG CLC SPI I2C UART DSM IOC Interrupt CAN FD CRC on Boot JTAG Basic

RA0

2 17 19 21

ANA0

C1IN0-

C2IN0-

CLCIN0(1)

CLCIN4(1)

IOCA0

TMS

RA1

3 18 20 22

ANA1

C1IN1-

C2IN1-

CLCIN1(1)

CLCIN5(1)

IOCA1

RA2

4 19 21 23

ANA2

DAC1OUT1

VREF- (DAC)

VREF- (ADC)

C1IN0+

C2IN0+

IOCA2

BOOTA2

RA3

5 20 22 24

ANA3

VREF+ (DAC)

VREF+ (ADC)

C1IN1+

MDCARL(1)

IOCA3

RA4

6 21 23 25 ANA4 T0CKI(1) SS2(1) CTS5(1)

MDCARH(1)

IOCA4

BOOTA4

RA5

7 22 24 26

ANA5

SS1(1) RX5(1)

MDSRC(1)

IOCA5

TCK

RA6

14 29 31 33

ANA6

CTS3(1)

IOCA6

CLKOUT

OSC2

RA7

13 28 30 32

ANA7

RX3(1)

IOCA7

OSC1

CLKIN

RB0

33 8 8 8

ANB0

C2IN1+

ZCDIN

CWG1(1)

IOCB0

INT0(1)

RB1 34 9 9 9 ANB1

C1IN3-

C2IN3-

CWG2(1)

(4)

IOCB1

INT1(1)

RB2 35 10 10 10 ANB2

CWG3(1)

SDI2(1) (4)

IOCB2

INT2(1)

RB3 36 11 11 11 ANB3

C1IN2-

C2IN2-

SCK2(1) IOCB3 CANRX(1) TDO
RB4 37 12 14 16

ANB4

ADACT(1)

T5G(1) CTS4(1) IOCB4
RB5 38 13 15 17 ANB5 T1G(1) CCP3(1) RX4(1) IOCB5 TDI
RB6 39 14 16 18 ANB6

CLCIN2(1)

CLCIN6(1)

CTS2(1) IOCB6 ICSPCLK
RB7 40 15 17 19 ANB7 DAC1OUT2 T6IN(1) PWM3ERS(1)

CLCIN3(1)

CLCIN7(1)

RX2(1) IOCB7 ICSPDAT
RC0 15 30 32 34 ANC0

T1CKI(1)

T3CKI(1)

T3G(1)

SMT1WIN(1)

IOCC0 SOSCO
RC1 16 31 35 35 ANC1 SMT1SIG(1) CCP2(1) IOCC1 SOSCIN

SOSCI

RC2 17 32 36 40 ANC2 T5CKI(1)

PWMIN0(1)

CCP1(1)

IOCC2
RC3 18 33 37 41 ANC3 T2IN(1) PWM1ERS(1) SCK1(1) SCL1(3,4) IOCC3
RC4 23 38 42 46 ANC4 SDI1(1) SDA(3,4) IOCC4 BOOTC4
RC5 24 39 43 47 ANC5 T4IN(1) PWM2ERS(1) IOCC5 BOOTC5
RC6 25 40 44 48 ANC6 PWMIN1(1) CTS1(1) IOCC6
RC7 26 1 1 1 ANC7 RX1(1) IOCC7
RD0 19 34 38 42 AND0
RD1 20 35 39 43 AND1
RD2 21 36 40 44 AND2
RD3 22 37 41 45 AND3
RD4 27 2 2 2 AND4
RD5 28 3 3 3 AND5
RD6 29 4 4 4 AND6
RD7 30 5 5 5 AND7
RE0 8 23 25 27 ANE0
RE1 9 24 26 28 ANE1
RE2 10 25 27 29 ANE2
RE3 1 16 18 20 IOCE3 Vpp/MCLR
RF0 36 ANF0
RF1 37 ANF1
RF2 38 ANF2
RF3 39 ANF3
RF4 12 ANF4
RF5 13 ANF5
RF6 14 ANF6
RF7 15 ANF7
VSS 12, 31 6, 27 6, 29 6,31 VSS
VDD(5) 11, 32 7, 26 7, 28 7, 30 VDD(5)
OUT(2)

ADGRDA

ADGRDB

C1OUT

C2OUT

TMR0

PWM11

PWM12

PWM21

PWM22

PWM31

PWM32

CCP1

CCP2

CCP3

CWG1A

CWG1B

CWG1C

CWG1D

CWG2A

CWG2B

CWG2C

CWG2D

CWG3A

CWG3B

CWG3C

CWG3D

CLC1OUT

CLC2OUT

CLC3OUT

CLC4OUT

CLC5OUT

CLC6OUT

CLC7OUT

CLC8OUT

SS1

SCK1

SDO1

SS2

SCK2

SDO2

SDA1

SCL1

DTR1

RTS1

TX1

DTR2

RTS2

TX2

DTR3

RTS3

TX3

DTR4

RTS4

TX4

DTR5

RTS5

TX5

DSM1 CANTX
Note:
  1. This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. Refer to the peripheral input selection table for details on which PORT pins may be used for this signal.
  2. All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options as described in the peripheral output selection table.
  3. This is a bidirectional signal. For normal module operation, the firmware needs to map this signal to the same pin in both the PPS input and PPS output registers.
  4. These pins are configured for I2C logic levels; The SCLx/SDAx signals may be assigned to any of these pins. PPS assignments to the other pins (e.g., RB1) will operate, but input logic levels will be standard TTL/ST as selected by the INLVL register, instead of the I2C specific or SMBus input buffer thresholds.
  5. A 0.1 uF bypass capacitor to VSS is required on all VDD pins.