3.3.3 Octal Serial Flash
The SAMA7G54-EK board features one Quad Serial Peripheral Interface (QSPI) memory MX66LM1G45GXDI00.
The QSPI is a synchronous serial data link that provides communication with external devices in Host mode.
The QSPI can be used in SPI mode to interface to serial peripherals (such as ADCs, DACs, LCD controllers, CAN controllers and sensors), or in Serial Memory mode to interface to serial Flash memories. Octal SPI mode is then used.
Using the QSPI, the system executes code directly from a serial Flash memory (XIP) without code shadowing to RAM. The serial Flash memory mapping is seen in the system as other memories such as ROM, SRAM, DRAM, embedded Flash memory, etc.
With the support of the Quad SPI protocol, the system can use high-performance serial Flash memories which are small and inexpensive compared to parallel Flash memories.
| PIO | Signal Name | Shared PIO | Signal Description |
|---|---|---|---|
| PB9 | QSPI0_IO3_PB9 | – | QSPI0 I/O line 3 |
| PB10 | QSPI0_IO2_PB10 | – | QSPI0 I/O line 2 |
| PB11 | QSPI0_IO1_PB11 | – | QSPI0 I/O line 1 |
| PB12 | QSPI0_IO0_PB12 | – | QSPI0 I/O line 0 |
| PB13 | QSPI0_CS | – | QSPI0 Chip Select |
| PB14 | QSPI0_DDR_CK_P | – | QSPI0 serial clock |
| PB16 | QSPI0_IO4_PB16 | – | QSPI0 I/O line 4 |
| PB17 | QSPI0_IO5_PB17 | – | QSPI0 I/O line 5 |
| PB18 | QSPI0_IO6_PB18 | – | QSPI0 I/O line 6 |
| PB19 | QSPI0_IO7_PB19 | – | QSPI0 I/O line 7 |
| PB20 | QSPI0_DQS_PB20 | – | QSPI00 data strobe |
| PB21 | QSPI0_INT_PB21 | – | QSPI0 interrupt |
| nRST/NRST_OUT | RESET# | – | Reset line from processor or from general reset |