3 Pin Description
The following figure illustrates the pin details of the ATA5296 device.
The following table provides the pin description of the ATA5296. Care must be taken to ensure that pin voltages are kept within the limits specified for the voltage domain to which they belong.
| Pin Number | Pin Name | Function | Remarks | Voltage Domain |
|---|---|---|---|---|
| Heat Slug | GND | Backside ground connection | — | GND |
| 1 | XTAL2 | Optional crystal connection 2, pin must be connected to GND if not used | — | AVCC18 |
| 2 | XTAL1 | Optional crystal connection 1, pin must be connected to GND if not used | — | AVCC18 |
| 3 | AVCC33 | 3.3V analog supply voltage capacitor connection | — | — |
| 4 | RSENSE | Connection for 1.2 kΩ reference resistor. Used for internal current measurements | — | AVCC33 |
| 5 | AGND | Dedicated ground for analog supply | — | — |
| 6 | VS2 | Battery supply voltage input | — | VS |
| 7 | A02 | Antenna driver output | — | VDS |
| 8 | VDS0 | Supply voltage for A0x drivers | — | VDS |
| 9 | NC | Can be left open or connected to GND | — | — |
| 10 | NC | Can be left open or connected to GND | — | — |
| 11 | VDRV | Driver support circuitry 3.3V supply voltage | — | — |
| 12 | RXINN | Immobilizer negative polarity receiver input | — | VTX |
| 13 | RXINP | Immobilizer positive polarity receiver input | — | VTX |
| 14 | VTX | Low noise 16V supply for immobilizer operation | — | — |
| 15 | A31 | Antenna driver output | — | VDS |
| 16 | VDS3 | Supply voltage for A3x drivers | — | — |
| 17 | A30 | Antenna driver output | — | VDS |
| 18 | NRES | Chip reset input pin. NRES = 0 for more than TNRES resets the chip. NRES = 1 enables the device | Digital input | VIF |
| 19 | NCS | SPI chip select input pin, active low | Digital pin | VIF |
| 20 | MOSI | Master-Out-Slave-In SPI input pin, data input in transparent mode | Digital input | VIF |
| 21 | MISO | Master-In-Slave-Out SPI output pin, data output in transparent mode, tri-state in IdleMode if NCS = 1 | Digital output | VIF |
| 22 | SCLK | SPI clock input pin | Digital input | VIF |
| 23 | GPIO0 | Configurable I/O pin, able to provide MACT, BCNT, CLKOUT, IRQ and other digital I/Os Default: GPIO (input) | Digital pin | VIF |
| 24 | GPIO1 | Configurable I/O pin, able to provide MACT, BCNT, CLKOUT, IRQ and other digital I/Os Default: GPIO (input) | Digital pin | VIF |
| 25 | IRQ (GPIO2) | Configurable I/O pin, able to provide MACT, BCNT, CLKOUT, IRQ and other digital I/Os Default: IRQ (Interrupt request output pin) | Digital pin | VIF |
| 26 | CLKOUT (GPIO3) | Configurable I/O pin, able to provide MACT, BCNT, CLKOUT, IRQ and other digital I/Os Default: Tristate input with CLKOUT preselected on the signal multiplexor | Digital pin | VIF |
| 27 | VIF | Interface supply voltage input | — | — |
| 28 | IFGND | Reference GND interface supply voltage input | — | — |
| 29 | NC | Can be left open or connected to GND | — | — |
| 30 | A21 | Antenna driver output | — | VDS |
| 31 | VDS2 | Supply voltage for A2x drivers | — | — |
| 32 | NC | Can be left open or connected to GND | — | — |
| 33 | DH5 | Door handle interface | — | VDH5 |
| 34 | DH4 | Door handle interface | — | VDH4 |
| 35 | DH3 | Door handle interface | — | VDH3 |
| 36 | DH2 | Door handle interface | — | VDH2 |
| 37 | DH1 | Door handle interface | — | VDH1 |
| 38 | DH0 | Door handle interface | — | VDH0 |
| 39 | VS1 | Battery supply voltage input | — | — |
| 40 | BCG | Boost converter gate connection to drive the gate of an external power MOSFET | — | VS |
| 41 | BCS | Boost converter source connection, current sense input connected to boost converter current sense resistor (Kelvin contact) | — | AVCC33 |
| 42 | BSENSE | Boost converter sense connection, connected to boost converter current sense resistor (Kelvin contact) | — | AVCC33 |
| 43 | A11 | Antenna driver output | — | VDS |
| 44 | VDS1 | Supply voltage for A1x drivers | — | — |
| 45 | A10 | Antenna driver output | — | VDS |
| 46 | DGND | Digital ground | — | — |
| 47 | DVCC | Digital supply voltage | — | — |
| 48 | AVCC18 | 1.8V analog supply voltage capacitor connection | — | — |