2.2.1 Starting Conversion

In Single Conversion mode, a conversion is triggered by writing a '1' to the ADC Start Conversion bit (STCONV) in the Command register (ADC.COMMAND). This bit is '1' as long as the conversion is in progress, and will be cleared when the conversion is completed. If a different input channel is selected while a conversion is in progress, the ADC will finish the current conversion before changing the channel.

In Free-Running mode, the first conversion is started by writing the STCONV bit to '1' in ADC.COMMAND. A new conversion cycle is started immediately after the previous conversion cycle has completed. The Result Ready flag (RESRDY) in the Interrupt Flag register (ADC.INTFLAG) is set.

If the Result Ready Interrupt Enable (RESRDY) bit in the Interrupt Control (ADC.INTCTRL) register and the Global Interrupt Enable bit in the CPU Status register (CPU_SREG.I) are '1', the Result Ready Interrupt vector will be executed.

The RESRDY Interrupt flag in ADC.INTFLAG will be set, even if the specific interrupt is disabled, allowing software to check for finished conversion by polling the flag. A conversion can thus be triggered without causing an interrupt.

Alternatively, a conversion can be triggered by an event. This is enabled by writing a '1' to the Start Event Input bit (STARTEI) in the Event Control register (ADC.EVCTRL). Any incoming event routed to the ADC through the Event System (EVSYS) will trigger an ADC conversion. This provides a method to start conversions at predictable intervals or at specific conditions. The event trigger input is edge sensitive. When an event occurs, STCONV in ADC.COMMAND is set. STCONV will be cleared when the conversion is complete.