17.6 Latency

The time between interrupt generation and the execution of the first instruction of your ISR is known as interrupt latency. There are two elements that affect it.

• Processor Servicing of Interrupt - This is the amount of time it takes the processor to recognize the interrupt and branch to the associated ISR.
• Saving ISR Code Context - The amount of time it takes to save registers on the stack before entering the ISR.

For the most part, these are determined solely by the hardware on Cortex-M devices. In particular, the hardware saves the context on the stack, eliminating the need for the compiler to generate such code. As a result, if your ISR is written such that it does not need to save any registers beyond what is saved by the hardware, the interrupt latency for your ISR is entirely hardware dependent.

On Cortex-A devices, the time taken by context saving is dependent on the number of registers saved on entry, which is determined by the code making up the function. This time has to be determined on a case-by-case basis, if required.

To determine the value of the interrupt latency, see the data sheet for your device and the appropriate technical reference manual.