2 Pin Descriptions

The descriptions of the pins are listed in Table 2-1.

Table 2-1. Pin Function Table
Name	32‑Lead CERDIP	32-Lead CLCC	32-Lead FLATPACK	30‑Pin PGA	Function
DC	—	1	—	—	Don’t Connect
A14	1	2	1	1	Address
A12	2	3	2	2	Address
A7	3	4	3	3	Address
A6	4	5	4	4	Address
A5	5	6	5	5	Address
A4	6	7	6	6	Address
A3	7	8	7	7	Address
A2	8	9	8	8	Address
A1	9	10	9	9	Address
A0	10	11	10	10	Address
NC	—	12	—	—	No Connect
I/O0	11	13	11	11	Data Input/Output
I/O1	12	14	12	12	Data Input/Output
I/O2	13	15	13	13	Data Input/Output
GND	14	16	14	14	Ground
DC	—	17	—	—	Don’t Connect
I/O3	15	18	15	15	Data Input/Output
I/O4	16	19	16	16	Data Input/Output
I/O5	17	20	17	17	Data Input/Output
I/O6	18	21	18	18	Data Input/Output
I/O7	19	22	19	19	Data Input/Output
CE	20	23	20	20	Chip Enable
A10	21	24	21	21	Address
OE	22	25	22	22	Output Enable
NC	—	26	—	—	No Connect
A11	23	27	23	23	Address
A9	24	28	24	24	Address
A8	25	29	25	25	Address
A13	26	30	26	26	Address
WE	27	31	27	27	Write Enable
V_CC	28	32	28	28	Device Power Supply

AT28C256