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     Features 
    
        
            Fast Read Access Time: 150 ns  
            Automatic Page Write Operation:
                    Internally organized as 32,768  x 8 (256K ) 
                    Internal address and data
                        latches for 64
                                                  bytes  
                    Internal control timer 
                  
            Fast Write Cycle Time:
                    Page Write cycle time: 3 ms or
                                                  10 ms  maximum 
                    1 to
                                                  64-byte  Page Write operation 
                  
            Low-Power Dissipation:
                    50 mA  active current 
                    300 µA  CMOS standby current 
                  
            Hardware and Software Data
                Protection 
            DATA  Polling for
                End of Write Detection 
            High Reliability CMOS Technology:
                    Endurance: 10,000 or 100,000
                        cycles 
                    Data retention: 10 years 
                  
            Single 5V ± 10% Supply 
            CMOS and TTL Compatible Inputs and
                Outputs 
            JEDEC®  Approved Byte-Wide
                Pinout 
         
     
  
                        
                        
                        
                        
                        
                        
                     
                    
                 
             
            
            
            
          
        The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.