The TWI supports several transmission modes with different frequency limitations:
Standard mode (Sm) up to 100
kHz
Fast mode (Fm) up to 400 kHz
Fast mode Plus (Fm+) up to 1
MHz
The Host Baud Rate (TWIn.MBAUD) register must be written to a value that results in
a TWI bus clock frequency equal to or less than those frequency limits, depending on the
transmission mode.
The low (tLOW) and high (tHIGH) times are determined by the Host Baud Rate (TWIn.MBAUD) register, while
the rise (tR) and fall (tOF) times are determined by
the bus topology.
Figure 29-3. SCL Timing
tLOW is the low period of the SCL clock
tHIGH is the high period of the SCL
clock
tR is determined by the bus impedance and the
internal pull-ups. Refer to Electrical Characteristics for details.
tOF is the output fall time determined by the
open-drain current limit and bus impedance. Refer to Electrical
Characteristics for details.
Properties of the SCL Clock
The SCL frequency is given
by:
The SCL clock is designed to have a 50/50 duty cycle, where the low period of the
duty cycle comprises tOF and tLOW. tHIGH will not
start until a high state of SCL has been detected. The following formula relates the
BAUD bit field in the TWIn.MBAUD register and the SCL frequency:
Equation 1 can be transformed to express BAUD:
Calculation of the BAUD Value
To ensure operation within the specifications of the desired speed mode
(Sm, Fm, Fm+), follow these steps:
Calculate a value for the
BAUD bit field using Equation 2.
Calculate tLOW
using the BAUD value from step 1:
Check if your tLOW
from Equation 3 is above the specified minimum of the desired mode
(tLOW_Sm= 4700 ns, tLOW_Fm= 1300 ns,
tLOW_Fm+= 500 ns)
If the calculated
tLOW is above the limit, use the BAUD value from
Equation 2
If the limit is not
met, calculate a new BAUD value using Equation 4 below, where
tLOW_mode is either tLOW_Sm,
tLOW_Fm, or tLOW_Fm+ from the mode
specifications: