23.3.5 Interrupts

Table 23-5. Available Interrupt Vectors and Sources in Single Mode
Vector Name	Source Name	Condition	Dependency
TCAn_OVF	OVF	The counter has reached TOP or BOTTOM	-
TCAn_CMP0	CMP0	Match between the counter value and the Compare 0 register	-
TCAn_CMP1	CMP1	Match between the counter value and the Compare 1 register	-
TCAn_CMP2	CMP2	Match between the counter value and the Compare 2 register	-

Table 23-6. Available Interrupt Vectors and Sources in Split Mode
Vector Name	Source Name	Conditions	Dependency
TCAn_OVF	LUNF	Low byte timer reaches BOTTOM	-
TCAn_HUNF	HUNF	High byte timer reaches BOTTOM	-
TCAn_CMP0	LCMP0	Match between the counter value and the low byte of the Compare 0 register	-
TCAn_CMP1	LCMP1	Match between the counter value and the low byte of the Compare 1 register	-
TCA_CMP2	LCMP2	Match between the counter value and the low byte of the Compare 2 register	-

When an interrupt condition occurs, the corresponding interrupt flag is set in the peripheral’s Interrupt Flags (peripheral.INTFLAGS) register.

An interrupt source is enabled or disabled by writing to the corresponding enable bit in the peripheral’s Interrupt Control (peripheral.INTCTRL) register.

An interrupt request is generated when the corresponding interrupt source is enabled, and the interrupt flag is set. The interrupt request remains active until the interrupt flag is cleared. See the peripheral’s INTFLAGS register for details on how to clear interrupt flags.