25.3.2.3.1 Transmit Pipeline

Before writing data to the Transmit Data (USARTn.TXDATA) registers, one must always check that the Data Register Empty (DREIF) interrupt flag is set to ‘1’ to avoid overwriting the buffer and losing data. Since the transmitter is double buffered, this can be handled in two different ways.

In cases where it is important that the data are transmitted back-to-back with no delay between frames, the DREIF interrupt flag should be polled or the corresponding interrupt enabled. When data are written immediately after DREIF is set, the pipeline always has a new byte to transmit directly after the previous byte is shifted out. This results in each frame being transmitted with no delay between the stop bit of the previous frame and start bit of the next frame.

When a delay between frames is acceptable and it is important that the CPU is not interrupted too often, the Transmit Complete (TXCIF) interrupt flag can be used. When the TXCIF flag is set to ‘1’, the entire pipeline, including the shift register is empty. At that point, software can alternate between checking DREIF and writing data. When DREIF is no longer ‘1’, the pipeline is full and subsequently transmits the written bytes.

Note:
  1. It may take up to one baud clock cycle for data to be shifted from the transmit buffer to the transmit shift register. This implies that two bytes can be written into an empty buffer back-to-back, while the third byte can be written only after the first byte has been loaded into the shift register.