30.3.4 Sleep Mode Operation

Writing the Run In Standby (RUNSTDBY) bit in the Control A (CCL.CTRLA) register to ‘1’ allows the selected clock source to be enabled in Standby sleep mode.

If RUNSTDBY is ‘0’, the peripheral clock is disabled in Standby sleep mode. If the filter, edge detector, and/or sequencer are enabled, the LUT output is forced to ‘0’ in Standby sleep mode. In Idle sleep mode, the TRUTH table decoder will continue the operation, and the LUT output will be refreshed accordingly, regardless of the RUNSTDBY bit.

If the Clock Source (CLKSRC) bit in the LUT n Control A (CCL.LUTnCTRLA) register is written to ‘1’, the LUTn-TRUTHSEL[2] always clocks the filter, edge detector, and sequencer. The availability of the LUTn-TRUTHSEL[2] clock in sleep modes depends on the sleep settings of the peripheral used.