25.4.2 Receiver Data Register High Byte
This register contains the MSb of the data received by the USART receiver, as well as status bits reflecting the status of the received data frame. The USART receiver is double-buffered, and this register always represents the data and status bits for the oldest received frame. If the data and status bits for only one frame are present in the receive buffer, this register contains that data.
The buffer shifts out the data either when RXDATAL or RXDATAH is read, depending on the configuration. The registerthat does not cause the data to be shifted must be read first to allow both bytes to be read before shifting occurs.
When the Character Size (CHSIZE) bits in the Control C (USARTn.CTRLC) register are configured to 9-bit (low byte first), reading RXDATAH shifts the receive buffer; otherwise, reading RXDATAL shifts the buffer.
| Name: | RXDATAH |
| Offset: | 0x01 |
| Reset: | 0x00 |
| Property: | – |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RXCIF | BUFOVF | FERR | PERR | DATA8 | |||||
| Access | R | R | R | R | R | ||||
| Reset | 0 | 0 | 0 | 0 | 0 |
Bit 7 – RXCIF USART Receive Complete Interrupt Flag
This flag is set when there are unread data in the receive buffer and cleared when the receive buffer is empty.
Bit 6 – BUFOVF Buffer Overflow
This flag is set if the data in the Receiver Data (USARTn.RXDATAL and USARTn.RXDATAH) registers has overwritten one or more frames. This occurs when the receive buffer is full, a new frame is waiting in the receive shift register, and a new Start bit is detected.
This flag is cleared when the USARTn.RXDATA registers are read.
This flag is not used in SPI Host mode of operation.
Bit 2 – FERR Frame Error
This flag is set if the first Stop bit of the frame in USARTn.RXDATA is
‘0’ and is cleared when it is correctly read as
‘1’.
This flag is not used in SPI Host mode of operation.
Bit 1 – PERR Parity Error
This flag is set if parity checking is enabled and the data in USARTn.RXDATA has a parity error; otherwise, this flag is cleared. For details on parity calculation, refer to Parity.
This flag is not used in SPI Host mode of operation.
Bit 0 – DATA8 Receiver Data Register
When using a 9-bit frame size, this bit holds the ninth bit (MSb) of the received data.
When the Receiver Mode (RXMODE) bit field in the Control B (USARTn.CTRLB) register is configured to LIN Constrained Auto-Baud (LINAUTO) mode, this bit indicates whether the received data are within the response space of a LIN frame. This bit is cleared if the received data are in the protected identifier field and is otherwise set.