15.5 Nesting Interrupts

The DSC devices support nested interrupts. Since processor resources are saved on the stack in an ISR, nested ISRs are coded in just the same way as non-nested ones. Nested interrupts are enabled by clearing the NSTDIS (nested interrupt disable) bit in the INTCON1 register. Note that this is the default condition as the 16-bit device comes out of Reset with nested interrupts enabled. Each interrupt source is assigned a priority in the Interrupt Priority Control registers (IPCn).

An interrupt is vectored if the priority of the interrupt source is greater than the current CPU priority level.