2 Memory Map

This section provides details on how the memory is organized for this device.

Table 2-1. Program Memory Map
AddressDevice
PIC16F18114 PIC16F18124 PIC16F18144 PIC16F18154 PIC16F18174PIC16F18115 PIC16F18125 PIC16F18145 PIC16F18155 PIC16F18175PIC16F18126 PIC16F18146 PIC16F18156 PIC16F18176
0000h to 0FFFhProgram Flash Memory (4 KW)(1)Program Flash Memory (8 KW)(1)Program Flash Memory (16 KW)(1)
1000h to 1FFFhNot Present(2)
2000h to 3FFFhNot Present(2)
4000h to 7FFFhNot Present(2)
8000h to 8003hUser IDs (4 Words)(3)
8004hReserved
8005hRevision ID (1 Word)(3)(4)(5)
8006hDevice ID (1 Word)(3)(4)(5)
8007h to 800BhConfiguration Words(3)
800Ch to 80FFhReserved
8100h to 813FhDevice Information Area (DIA)(3)(5)
8140h to 81FFhReserved
8200h to 82FFhDevice Configuration Information(3)(4)(5)
8300h to EFFFhReserved
F000h to F0FFhEEPROM
F100h to FFFFhReserved
Note:
  1. Storage Area Flash (SAF) is implemented as the last 128 words of Program Flash Memory, if enabled.
  2. The addresses do not roll over. The region is read as ‘0’. When accessing these areas using the NVMCON registers, reads and/or writes will set the NVMERR bit.
  3. Not code-protected.
  4. Hard-coded in silicon.
  5. This region cannot be written by the user, and is not affected by a Bulk Erase.