# 34 Instruction Set Summary

Table 34-1. Arithmetic and Logic Instructions
MnemonicOperandsDescriptionOpFlags#Clocks
SUBRd, RrSubtract without CarryRdRd - RrZ,C,N,V,S,H1
SUBIRd, KSubtract ImmediateRdRd - KZ,C,N,V,S,H1
SBCRd, RrSubtract with CarryRdRd - Rr - CZ,C,N,V,S,H1
SBCIRd, KSubtract Immediate with CarryRdRd - K - CZ,C,N,V,S,H1
SBIWRd, KSubtract Immediate from WordRd + 1:RdRd + 1:Rd - KZ,C,N,V,S2
ANDRd, RrLogical ANDRdRd • RrZ,N,V,S1
ANDIRd, KLogical AND with ImmediateRdRd • KZ,N,V,S1
ORRd, RrLogical ORRdRd v RrZ,N,V,S1
ORIRd, KLogical OR with ImmediateRdRd v KZ,N,V,S1
EORRd, RrExclusive ORRdRd ⊕ RrZ,N,V,S1
COMRdOne’s ComplementRd$FF - RdZ,C,N,V,S1 NEGRdTwo’s ComplementRd$00 - RdZ,C,N,V,S,H1
SBRRd,KSet Bit(s) in RegisterRdRd v KZ,N,V,S1
CBRRd,KClear Bit(s) in RegisterRdRd • ($FFh - K)Z,N,V,S1 INCRdIncrementRdRd + 1Z,N,V,S1 DECRdDecrementRdRd - 1Z,N,V,S1 TSTRdTest for Zero or MinusRdRd • RdZ,N,V,S1 CLRRdClear RegisterRdRd ⊕ RdZ,N,V,S1 SERRdSet RegisterRd$FFNone1
MULRd,RrMultiply UnsignedR1:R0Rd x Rr (UU)Z,C2
MULSRd,RrMultiply SignedR1:R0Rd x Rr (SS)Z,C2
MULSURd,RrMultiply Signed with UnsignedR1:R0Rd x Rr (SU)Z,C2
FMULRd,RrFractional Multiply UnsignedR1:R0Rd x Rr<<1 (UU)Z,C2
FMULSRd,RrFractional Multiply SignedR1:R0Rd x Rr<<1 (SS)Z,C2
FMULSURd,RrFractional Multiply Signed with UnsignedR1:R0Rd x Rr<<1 (SU)Z,C2
Table 34-2. Branch Instructions
MnemonicOperandsDescriptionOpFlags#Clocks
RJMPkRelative JumpPCPC + k + 1None2

PC(15:0)

PC(21:16)

←

Z

0

None2
JMPkJumpPCkNone3
RCALLkRelative Call SubroutinePCPC + k + 1None2 / 3
ICALLIndirect Call to (Z)

PC(15:0)

PC(21:16)

←

Z

0

None2 / 3
CALLkCall SubroutinePCkNone3 / 4
RETSubroutine ReturnPCSTACKNone4 / 5
RETIInterrupt ReturnPCSTACKI4 / 5
CPSERd,RrCompare, skip if Equalif (Rd = Rr) PCPC + 2 or 3None1 / 2 / 3
CPRd,RrCompareRd - RrZ,C,N,V,S,H1
CPCRd,RrCompare with CarryRd - Rr - CZ,C,N,V,S,H1
CPIRd,KCompare with ImmediateRd - KZ,C,N,V,S,H1
SBRCRr, bSkip if Bit in Register Clearedif (Rr(b) = 0) PCPC + 2 or 3None1 / 2 / 3
SBRSRr, bSkip if Bit in Register Setif (Rr(b) = 1) PCPC + 2 or 3None1 / 2 / 3
SBICA, bSkip if Bit in I/O Register Clearedif (I/O(A,b) = 0) PCPC + 2 or 3None1 / 2 / 3
SBISA, bSkip if Bit in I/O Register SetIf (I/O(A,b) =1) PCPC + 2 or 3None1 / 2 / 3
BRBSs, kBranch if Status Flag Setif (SREG(s) = 1) then PCPC + k + 1None1 / 2
BRBCs, kBranch if Status Flag Clearedif (SREG(s) = 0) then PCPC + k + 1None1 / 2
BREQ kBranch if Equalif (Z = 1) then PCPC + k + 1None1 / 2
BRNE kBranch if Not Equalif (Z = 0) then PCPC + k + 1None1 / 2
BRCS kBranch if Carry Setif (C = 1) then PCPC + k + 1None1 / 2
BRCC kBranch if Carry Clearedif (C = 0) then PCPC + k + 1None1 / 2
BRSH kBranch if Same or Higherif (C = 0) then PCPC + k + 1None1 / 2
BRLO kBranch if Lowerif (C = 1) then PCPC + k + 1None1 / 2
BRMI kBranch if Minusif (N = 1) then PCPC + k + 1None1 / 2
BRPL kBranch if Plusif (N = 0) then PCPC + k + 1None1 / 2
BRGE kBranch if Greater or Equal, Signedif (N ⊕ V= 0) then PCPC + k + 1None1 / 2
BRLT kBranch if Less Than, Signedif (N ⊕ V= 1) then PCPC + k + 1None1 / 2
BRHS kBranch if Half Carry Flag Setif (H = 1) then PCPC + k + 1None1 / 2
BRHC kBranch if Half Carry Flag Clearedif (H = 0) then PCPC + k + 1None1 / 2
BRTS kBranch if T Flag Setif (T = 1) then PCPC + k + 1None1 / 2
BRTC kBranch if T Flag Clearedif (T = 0) then PCPC + k + 1None1 / 2
BRVS kBranch if Overflow Flag is Setif (V = 1) then PCPC + k + 1None1 / 2
BRVC kBranch if Overflow Flag is Clearedif (V = 0) then PCPC + k + 1None1 / 2
BRIE kBranch if Interrupt Enabledif (I = 1) then PCPC + k + 1None1 / 2
BRID kBranch if Interrupt Disabledif (I = 0) then PCPC + k + 1None1 / 2
Table 34-3. Data Transfer Instructions
MnemonicOperandsDescriptionOpFlags#Clocks
MOVRd, RrCopy RegisterRdRrNone1
MOVWRd, RrCopy Register PairRd+1:RdRr+1:RrNone1
LDSRd, kLoad Direct from data spaceRd(k)None3(1)

Rd

X

←

(X)

X + 1

None2(1)

X

Rd

←

X - 1

(X)

None2(1)

Rd

Y

←

(Y)

Y + 1

None2(1)

Y

Rd

←

Y - 1

(Y)

None2(1)
LDDRd, Y+qLoad Indirect with DisplacementRd(Y + q)None2(1)

Rd

Z

←

(Z)

Z+1

None2(1)

Z

Rd

←

Z - 1

(Z)

None2(1)
LDDRd, Z+qLoad Indirect with DisplacementRd(Z + q)None2(1)
STSk, RrStore Direct to Data Space(k)RdNone2(1)
STX, RrStore Indirect(X)RrNone1(1)
STX+, RrStore Indirect and Post-Increment

(X)

X

←

Rr

X + 1

None1(1)
ST-X, RrStore Indirect and Pre-Decrement

X

(X)

←

X - 1

Rr

None1(1)
STY, RrStore Indirect(Y)RrNone1(1)
STY+, RrStore Indirect and Post-Increment

(Y)

Y

←

Rr

Y + 1

None1(1)
ST-Y, RrStore Indirect and Pre-Decrement

Y

(Y)

←

Y - 1

Rr

None1(1)
STDY+q, RrStore Indirect with Displacement(Y + q)RrNone1(1)
STZ, RrStore Indirect(Z)RrNone1(1)
STZ+, RrStore Indirect and Post-Increment

(Z)

Z

←

Rr

Z + 1
None1(1)
ST-Z, RrStore Indirect and Pre-DecrementZZ - 1None1(1)
STDZ+q,RrStore Indirect with Displacement(Z + q)RrNone1(1)
LPMRd, Z+Load Program Memory and Post-Increment

Rd

Z

←

(Z)

Z + 1

None3
INRd, AIn From I/O LocationRdI/O(A)None1
OUTA, RrOut To I/O LocationI/O(A)RrNone1
PUSHRrPush Register on StackSTACKRrNone1
POPRdPop Register from StackRdSTACKNone2
Table 34-4. Bit and Bit-Test Instructions
MnemonicOperandsDescriptionOpFlags#Clocks
LSLRdLogical Shift Left

Rd(n+1)

Rd(0)

C

Rd(n)

0

Rd(7)

Z,C,N,V,H1
LSRRdLogical Shift Right

Rd(n)

Rd(7)

C

Rd(n+1)

0

Rd(0)

Z,C,N,V1
ROLRdRotate Left Through Carry

Rd(0)

Rd(n+1)

C

C

Rd(n)

Rd(7)

Z,C,N,V,H1
RORRdRotate Right Through Carry

Rd(7)

Rd(n)

C

C

Rd(n+1)

Rd(0)

Z,C,N,V1
ASRRdArithmetic Shift RightRd(n)Rd(n+1), n=0..6Z,C,N,V1
SWAPRdSwap NibblesRd(3..0)Rd(7..4)None1
SBIA, bSet Bit in I/O RegisterI/O(A, b)1None1
CBIA, bClear Bit in I/O RegisterI/O(A, b)0None1
BSTRr, bBit Store from Register to TTRr(b)T1
BLDRd, bBit load from T to RegisterRd(b)TNone1
BSETsFlag SetSREG(s)1SREG(s)1
BCLRsFlag ClearSREG(s)0SREG(s)1
SECSet CarryC1C1
CLCClear CarryC0C1
SENSet Negative FlagN1N1
CLNClear Negative FlagN0N1
SEZSet Zero FlagZ1Z1
CLZClear Zero FlagZ0Z1
SEIGlobal Interrupt EnableI1I1
CLIGlobal Interrupt DisableI0I1
SESSet Signed Test FlagS1S1
CLSClear Signed Test FlagS0S1
SEVSet Two’s Complement OverflowV1V1
CLVClear Two’s Complement OverflowV0V1
SETSet T in SREGT1T1
CLTClear T in SREGT0T1
SEHSet Half Carry Flag in SREGH1H1
CLHClear Half Carry Flag in SREGH0H1
Table 34-5. MCU Control Instructions
MnemonicOperandsDescriptionOperationFlags#Clocks