40 Errata

Die Revision A


  1. Not possible to read SYSCFG.EXTBRK.ENABLE
    The SYSCFG.EXTBRK.ENABLE bit is not readable.


  1. False triggering when sweeping negative input of the AC when the low power mode is disabled
    A false trigger may occur if sweeping the negative input of the AC with a negative slope and the AC has low power mode disabled.
    Enable low power mode in AC.CTRLA.LPMODE
  2. AC interrupt flag not set unless interrupt is enabled
    ACn.STATUS.CMP is not set if the ACn.INTCTRL.CMP is not set.
    Enable ACn.INTCTRL.CMP or use ACn.STATUS.STATE for polling.


  1. SAMPDLY and ASDV does not work together with SAMPLEN
    Using SAMPCTRL.SAMPLEN at the same time as CTRLD.SAMPDLY or CTRLD.ASDV will cause an unpredictable sampling length.
    When setting SAMPCTRL.SAMPLEN greater than zero the CTRLD.SAMPDLY and CTRLD.ASDV must be cleared.
  2. ADC interrupt flag cleared when reading RESH
    ADCn.INTFLAGS.RESRDY and ADCn.INTFLAGS.WCOMP are cleared when reading ADCn.RESH.
    In 8-bit mode, read ADCn.RESH to clear the flag or clear the flag directly.
  3. Changing ADC control bits during free running mode not working
    If control signals are changed during free running mode, the new configuration is not properly taken into account in the next measurement. This is valid for registers ADC.CTRLB, ADC.CTRLC, ADC.SAMPCTRL and ADC.MUXPOS, ADC.WINLT and ADC.WINHT.
    Disable ADC free running mode before update of ADC.CTRLB, ADC.CTRLC, ADC.SAMPCTRL, ADC.MUXPOS, ADC.WINLT or ADC.WINHT.
  4. One extra measurement performed after disabling ADC free running mode
    The ADC may perform one additional measurement after clearing ADCn.CTRLA.FREERUN
    Write ADCn.CTRLA.ENABLE to zero to stop the free running mode immediately.


  1. TCB interrupt flag cleared when reading CCMPH
    TCBn.INTFLAGS.CAPT is cleared when reading TCBn.CCMPH instead of CCMPL.
    Read both TCBn.CCMPL and TCBn.CCMPH.
  2. TCB input capture frequency and pulse-width measurement mode not working with prescaled clock
    The TCB input capture frequency and pulse-width measurement mode may lock to freeze state if CLKSEL in TCB.CTRLA is set to other value than 0x0.
    Only use CLKSEL equal to 0x0 when using Input capture frequency and pulse-width measurement mode.


  1. TCD event output lines may give false events
    The TCD event output lines can give out false events.
    Use the delayed event functionality with minimum one cycle delay.
  2. TCD autoupdate not working
    The TCD autoupdate feature is not working.


  1. TIMEOUT bits in TWI.MCTRLB register is not accessible
    The TIMEOUT bits in TWI.MCTRLB register is not accessible from software.
    When initializing TWI, BUSSTATE in TWI.MSTATUS should be brought into IDLE state by writing 0x1 to it.
  2. TWI Master Mode wrongly detect start bit as a stop bit
    If TWI is enabled in master mode followed by an immediate write to the MADDR register, the bus monitor recognize the start bit as a stop bit.
    Wait minimum two clock cycles from TWI.MCTRLA.ENABLE until TWI.MADDR is written.
  3. TWI Smart Mode gives extra clock pulse
    TWI Master with Smart Mode enabled gives an extra clock pulse on SCL line after sending NACK.
  4. TWI Master Enable Quick Command not accessible
    TWI.MCTRLA.QCEN is not accessible from software.


  1. Frame error on previous message may cause false start bit detection
    If receiving a frame with RXDATAH.FERR set and reading the RXDATAL before the RxD line goes high, will trigger a false start bit detection.
    Wait for the RxD pin to go high before reading RXDATA, for instance by polling the bit in PORTn.IN where the RxD pin is located.