TA100 B6 Errata
This document describes errata items identified in the B6 version of TA100 silicon.
The table below lists all B6 devices impacted by these changes.
| Ordering Code | Description | Personalization |
|---|---|---|
| TA100T-Y240C2X01-00T-VAO | 8-pin SOIC, with I2C Interface in Tape and Reel | Standard Configuration |
| TA100T-Y240C2X01-00B-VAO | 8-pin SOIC, with I2C Interface in Bulk | Standard Configuration |
| TA100-Y240C2X01-00T-VAO | 8-pin SOIC, with SPI Interface in Tape and Reel | Standard Configuration |
| TA100-Y240C2X01-PDT-VAO | 8-pin SOIC, with SPI Interface in Tape and Reel | SPI Pull-ups Disabled |
| TA100-Y240C2X01-00B-VAO | 8-pin SOIC, with SPI Interface in Bulk | Standard Configuration |
| TA100-Y240C2X01-PDB-VAO | 8-pin SOIC, with SPI Interface in Bulk | SPI Pull-ups Disabled |
| TA100-240UFB01-00T-VAO | 24-pad VQFN, with SPI and I2C Interface in Tape and Reel | Standard Configuration |
| TA100-240UFB01-00B-VAO | 24-pad VQFN, with SPI and I2C Interface in Bulk | Standard Configuration |
Note: Patch P5 is released as
public silicon.