27.5.5 USART Status Register


Bit	7	6	5	4	3	2	1	0
	RXCIF	TXCIF	DREIF	RXSIF	ISFIF		BDF	WFB
Access	R	R/W	R	R/W	R/W		R/W	W
Reset	0	0	1	0	0		0	0

Bit 7 – RXCIF USART Receive Complete Interrupt Flag

This flag is set when there are unread data in the receive buffer and cleared when the receive buffer is empty.

Bit 6 – TXCIF USART Transmit Complete Interrupt Flag

This flag is set when the entire frame in the transmit shift register has been shifted out, and there are no new data in the transmit buffer (TXDATAL and TXDATAH) registers. It is cleared by writing a ‘1’ to it.

Bit 5 – DREIF USART Data Register Empty Interrupt Flag

This flag is set when the Transmit Data (USARTn.TXDATAL and USARTn.TXDATAH) registers are empty and cleared when they contain data not yet moved into the transmit shift register.

Bit 4 – RXSIF USART Receive Start Interrupt Flag

This flag is set when Start-of-Frame detection is enabled, the device is in Standby sleep mode, and a valid start bit is detected. It is cleared by writing a ‘1’ to it.

This flag is not used in the Host SPI mode operation.

Bit 3 – ISFIF Inconsistent Synchronization Field Interrupt Flag

This flag is set if an auto-baud mode is enabled, and the synchronization field is too short or too long to give a valid baud setting. It will also be set when USART is set to LINAUTO mode, and the SYNC character differs from data value 0x55. This flag is cleared by writing a ‘1’ to it. See the Auto-Baud section for more information.

Bit 1 – BDF Break Detected Flag

This flag is set if an auto-baud mode is enabled and a valid break and synchronization character is detected, and is cleared when the next data are received. It can also be cleared by writing a ‘1’ to it. See the Auto-Baud section for more information.

Bit 0 – WFB Wait For Break

Setting this bit enables the Wait For Break feature for the following incoming frame. After this frame, the feature is automatically disabled.

Name:	STATUS
Offset:	0x04
Reset:	0x20
Property:	-