31.5.7 LUT n Control B

Note:

SPI connections to the CCL work in Host SPI mode only.
USART connections to the CCL work only when the USART is in one of the following modes:
- Asynchronous USART
- Synchronous USART host

Name:	LUTnCTRLB
Offset:	0x09 + n*0x04 [n=0..3]
Reset:	0x00
Property:	Enable-Protected


Bit	7	6	5	4	3	2	1	0
	INSEL1[3:0]				INSEL0[3:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 7:4 – INSEL1[3:0] LUT n Input 1 Source Selection

These bits select the source for input 1 of LUT n.


Value	Name	Description
`0x00`	MASK	Masked input
`0x01`	FEEDBACK	Feedback input
`0x02`	LINK	Output from LUT(n+1) as input source
`0x03`	EVENTA	Event A as input source
`0x04`	EVENTB	Event B as input source
`0x05`	IN1	IN1 input source
`0x06`	AC1	AC1 OUT input source
`0x07`	USART0	USART0 TXD input source
`0x08`	SPI0	SPI0 MOSI input source
`0x09`	TCE0	TCE0 WO1 input source
`0x0A`	TCB1	TCB1 WO input source
`0x0B`	TCF0	TCF0 WO1 input source
`0x0C`	WEX0	WEX Fault Blanking input source
`Other`	-	Reserved

Bits 3:0 – INSEL0[3:0] LUT n Input 0 Source Selection

These bits select the source for input 0 of LUT n.


Value	Name	Description
`0x00`	MASK	Masked input
`0x01`	FEEDBACK	Feedback input
`0x02`	LINK	Output from LUT(n+1) as input source
`0x03`	EVENTA	Event A as input source
`0x04`	EVENTB	Event B as input source
`0x05`	IN0	IN0 input source
`0x06`	AC0	AC0 OUT input source
`0x07`	USART0	USART0 TXD input source
`0x08`	SPI0	SPI0 MOSI input source
`0x09`	TCE0	TCE0 WO0 input source
`0x0A`	TCB0	TCB0 WO input source
`0x0B`	TCF0	TCF0 WO0 input source
`0x0B`	WEX0	WEX Fault Blanking input source
`Other`	-	Reserved

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