2.2.2 Filter

To be sure to remove all glitches, the filter options may be selected if the user wants to avoid spikes and glitches that affect the system. The filter will first run the signal through the two-stage synchronizer and then further through the filter.

The XNOR acts as a majority vote and as long as the inputs to the XNOR are different from each other, the output will be ‘0’.
  • If the two XNOR inputs are equal, its output is ‘1’
  • If the XNOR output is ‘1’, the gate input on the last D flip-flop is high
  • If the XNOR output is ‘0’, the gate input on the last D flip-flop is low
When a filter is enabled, the output will be delayed up to four CLK cycles. Using these options, any output from the LUT shorter than two synchronized clock cycles will be filtered out.

Sometimes, based on the logic values used as inputs to the LUT, a valid output signal can be high for a few clock cycles. If the filter option is chosen in such cases, it will break the function of the system by filtering out valid signals. The filter may only be used when it does not matter if the signal is delayed or shortened by the filter. Before implementing any of the filter options, it would be recommended to analyze what is the shortest valid signal out of the LUT in the current configuration. If the shortest signal is shorter than two cycles, a filter must not be used.

Figure 2-15. Filter
Figure 2-16. Filter timing