Hardware Description Language: Use the powerful and easy-to-learn CUPL language
created for SPLDs and CPLDs to describe complex logic with simple Boolean equations,
truth tables and state machines.
Integrated Development Environment:
Seamlessly write, compile and debug your designs without leaving the
application.
Built-in Functional Simulator: Test
and verify your logic with the included functional simulator before programming your
PLD, saving time and preventing errors.
Wide Device Support: Can be used with
all Microchip SPLDs and CPLDs.
Industry-Standard Output: Generate JEDEC programming files that are compatible with
virtually all Microchip and third-party device programmers.
DS20007127A
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
