6.1 Client Mode Transmission (7-Bit Addressing)

The following section describes the sequence of events when using the I2C in Client mode transmission.

  1. Host device issues a Start condition. Once the Start is detected, the client hardware sets the Start Condition Interrupt Flag (SCIF).
  2. Host transmits the 7-bit client address with R/W set.
  3. The received address is compared to the values in the I2CxADR registers.

    If the client is configured in 7-bit Addressing mode (no masking), the received address is independently compared to each of the I2CxADR0/1/2/3 registers. In 7-bit Addressing mode with masking, the received address is masked with the value in the I2CxADR1 and I2CxADR3 and compared to the value of I2CxADR0 and I2CxADR2.

    If a match occurs, the Client Mode Active (SMA) bit is set, the R/W bit information (bit ‘0’ of the matching address) is transferred to the Read Information (R) bit of the I2CxSTAT0 register, the Data (D) bit of the I2CxSTAT0 register is cleared, and the Address Interrupt Flag (ADRIF) bit is set. If the ABD is cleared, the matching address is copied into the I2CxADB0 register. If ABD is set, the matching address is copied into the receive buffer, I2CxRXB, setting the Receive Buffer Full (RXBF) and I2C Receive Interrupt Flag (I2CxRXIF) bits. I2CRXIF is a read-only bit, and must be cleared by setting the Clear Buffer (CLRBF) bit or reading I2CxRXB.

    If there is not an address match, the module goes idle.

  4. When ADRIF is set, if the Address Interrupt and Hold Enable (ADRIE) bit is set and the Clock Stretching Disable (CSD) bit is cleared, client hardware sets the Client Clock Stretching (CSTR) bit, and the generic I2CxIF Flag bit. This allows time for the client to read either I2CxADB0 or I2CxRXB and selectively ACK/NACK based on the received address. When the client has finished processing the address, the software clears CSTR and ADRIF, which releases the clock and clears the I2CxIF Flag bit.
  5. If TXBE = 1, I2CxCNT has a non-zero value, and I2CxTXIF = 1, the client hardware sets CSTR, and waits for the software to load I2CxTXB. I2CxTXB must be loaded to clear I2CxTXIF and release SCL. I2CxCNT is decremented after the byte is transferred to the Shift register.
  6. Host transmits the 9th clock pulse, and the client hardware transfers the value of the ACKDT bit onto the SDA line. If there are pending errors, such as a receive overflow, the client hardware automatically generates a NACK sequence, NACKIF is set, and the module goes idle. The client hardware checks I2CxCNT. If I2CxCNT = 0, the Byte Count Interrupt Flag (CNTIF) is set.
  7. If the client issued an ACK and the I2CxCNT is non-zero, the host transmits eight clock pulses, and the client begins to shift out the data byte Most Significant Bit (MSb) first. If I2CxCNT = 0, CNTIF is set.
  8. Host receives data byte from client, then transmits an ACK/NACK sequence. The client hardware copies the ACK value into the Acknowledge Status (ACKSTAT) bit, and sets ACKTIF. If the Acknowledge Time Interrupt and Hold Enable (ACKTIE) bit is set, the client hardware sets the CSTR and I2CxIF bits. When the client is ready, the software clears the CSTR and ACKTIF bits, which releases SCL and clears I2CxIF.
  9. Steps 13-16 continue until the host has received all the requested data. Once all data are received, the host transmits a NACK condition followed by either a Stop condition or Restart condition. The client hardware sets NACKIF and PCIF, and clears SMA.